From 3f2fe6d28728c095ff737a01c99314a284e6e752 Mon Sep 17 00:00:00 2001
From: Flavio Alves <flavio.alves@phiinnovations.com>
Date: Thu, 14 Jun 2012 11:43:39 -0300
Subject: [PATCH] * Update x-load from the following git repository  
 git://git.gitorious.org/x-load-omap3/mainline.git   The
 main implementation is the generation of the MLO file  
 from PTXDIST

---
 patches/x-load-f243938/series                      |    1 +
 .../update-x_load-from-gitourious.patch            | 7077 ++++++++++++++++++++
 2 files changed, 7078 insertions(+)
 create mode 100644 patches/x-load-f243938/series
 create mode 100644 patches/x-load-f243938/update-x_load-from-gitourious.patch

diff --git a/patches/x-load-f243938/series b/patches/x-load-f243938/series
new file mode 100644
index 0000000..9fb2360
--- /dev/null
+++ b/patches/x-load-f243938/series
@@ -0,0 +1 @@
+update-x_load-from-gitourious.patch
diff --git a/patches/x-load-f243938/update-x_load-from-gitourious.patch b/patches/x-load-f243938/update-x_load-from-gitourious.patch
new file mode 100644
index 0000000..da722ad
--- /dev/null
+++ b/patches/x-load-f243938/update-x_load-from-gitourious.patch
@@ -0,0 +1,7077 @@
+diff -uNr x-load-f243938.orig/board/omap3530beagle/omap3530beagle.c x-load-f243938/board/omap3530beagle/omap3530beagle.c
+--- x-load-f243938.orig/board/omap3530beagle/omap3530beagle.c	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/board/omap3530beagle/omap3530beagle.c	2012-06-07 14:45:39.441648666 -0300
+@@ -304,7 +304,31 @@
+ 	/* setup sdrc to ball mux */
+ 	__raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
+ 
+-	if (beagle_revision() == REVISION_XM) {
++	switch(beagle_revision()) {
++	case REVISION_C4:
++		if (identify_xm_ddr() == NUMONYX_MCP) {
++			__raw_writel(0x4, SDRC_CS_CFG); /* 512MB/bank */
++			__raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_0);
++			__raw_writel(SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM, SDRC_MCFG_1);
++			__raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
++			__raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
++			__raw_writel(NUMONYX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
++			__raw_writel(NUMONYX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
++			__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
++			__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
++		} else {
++			__raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
++			__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
++			__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
++			__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
++			__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
++			__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
++			__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
++			__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
++			__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
++		}
++		break;
++	case REVISION_XM:
+ 		if (identify_xm_ddr() == MICRON_DDR) {
+ 			__raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
+ 			__raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
+@@ -326,7 +350,8 @@
+ 			__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
+ 			__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
+ 		}
+-	} else {
++		break;
++	default:
+ 		__raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
+ 		__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
+ 		__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
+@@ -659,7 +684,10 @@
+ 		printf("Beagle Rev C1/C2/C3\n");
+ 		break;
+ 	case REVISION_C4:
+-		printf("Beagle Rev C4\n");
++		if (identify_xm_ddr() == NUMONYX_MCP)
++			printf("Beagle Rev C4 from Special Computing\n");
++		else
++			printf("Beagle Rev C4\n");
+ 		break;
+ 	case REVISION_XM:
+ 		printf("Beagle xM Rev A\n");
+@@ -955,6 +983,7 @@
+ 	__raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
+ 	delay(1000);
+ 
++#ifdef CFG_NAND_K9F1G08R0A
+ 	if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
+ 		__raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ 		__raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+@@ -975,9 +1004,10 @@
+ #endif
+ 			return 1;
+ 		}
+-
+ 	}
++#endif
+ 
++#ifdef CFG_ONENAND
+ 	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
+ 		__raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ 		__raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+@@ -999,6 +1029,7 @@
+ 			return 1;
+ 		}
+ 	}
++#endif
+ 	return 0;
+ }
+ 
+diff -uNr x-load-f243938.orig/board/omap3evm/omap3evm.c x-load-f243938/board/omap3evm/omap3evm.c
+--- x-load-f243938.orig/board/omap3evm/omap3evm.c	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/board/omap3evm/omap3evm.c	2012-06-07 14:45:39.445648666 -0300
+@@ -235,7 +235,7 @@
+         	__raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
+ 	}
+ 
+-	__raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
++	__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
+ 	__raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
+ 
+ 	/* init sequence for mDDR/mSDR using manual commands (DDR is different) */
+diff -uNr x-load-f243938.orig/board/omap4430panda/clock.c x-load-f243938/board/omap4430panda/clock.c
+--- x-load-f243938.orig/board/omap4430panda/clock.c	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/board/omap4430panda/clock.c	2012-06-07 14:45:39.445648666 -0300
+@@ -0,0 +1,804 @@
++/*
++ * (C) Copyright 2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ * Rajendra Nayak <rnayak@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/cpu.h>
++#include <asm/io.h>
++#include <asm/arch/bits.h>
++#include <asm/arch/clocks.h>
++#include <asm/arch/mem.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/arch/sys_info.h>
++#include <asm/arch/clocks443x.h>
++#include <command.h>
++
++#define CONFIG_OMAP4_SDC 1
++
++/* Used to index into DPLL parameter tables */
++struct dpll_param {
++	unsigned int m;
++	unsigned int n;
++	unsigned int m2;
++	unsigned int m3;
++	unsigned int m4;
++	unsigned int m5;
++	unsigned int m6;
++	unsigned int m7;
++};
++
++/* Tables having M,N,M2 et al values for different sys_clk speeds
++ * This table is generated only for OPP100
++ * The tables are organized as follows:
++ * Rows : 1 - 12M, 2 - 13M, 3 - 16.8M, 4 - 19.2M, 5 - 26M, 6 - 27M, 7 - 38.4M
++ */
++
++/* MPU parameters */
++struct dpll_param mpu_dpll_param[7] = {
++	/* 12M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 13M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 16.8M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 19.2M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 26M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 27M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 38.4M values */
++#ifdef CONFIG_MPU_600
++	/* RUN MPU @ 600 MHz */
++	{0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
++#elif CONFIG_MPU_1000
++	{0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},
++#else
++	{0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00},	
++#endif
++};
++
++/* IVA parameters */
++struct dpll_param iva_dpll_param[7] = {
++	/* 12M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 13M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 16.8M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 19.2M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 26M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 27M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 38.4M values */
++#ifdef CONFIG_OMAP4_SDC
++	{0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00},
++#else
++	{0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00},
++#endif
++};
++
++/* CORE parameters */
++struct dpll_param core_dpll_param[7] = {
++	/* 12M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 13M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 16.8M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 19.2M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 26M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 27M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 38.4M values - DDR@200MHz*/
++	{0x7d, 0x05, 0x02, 0x05, 0x08, 0x04, 0x06, 0x05},
++};
++
++/* CORE parameters - ES2.1 */
++struct dpll_param core_dpll_param_ddr400[7] = {
++	/* 12M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 13M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 16.8M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 19.2M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 26M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 27M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 38.4M values - DDR@400MHz*/
++	{0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
++};
++
++/* CORE parameters for L3 at 190 MHz - For ES1 only*/
++struct dpll_param core_dpll_param_l3_190[7] = {
++	/* 12M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 13M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 16.8M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 19.2M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 26M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 27M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 38.4M values */
++#ifdef CONFIG_OMAP4_SDC
++#ifdef CORE_190MHZ 
++	{0x1f0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
++#else /* Default CORE @166MHz */
++	{0x1b0, 0x18, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05},
++#endif
++#else
++	{0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x08},
++#endif
++};
++
++/* PER parameters */
++struct dpll_param per_dpll_param[7] = {
++	/* 12M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 13M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 16.8M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 19.2M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 26M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 27M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 38.4M values */
++#if 0
++	/* SDC settings */
++	{0x0a, 0x00, 0x04, 0x03, 0x06, 0x05, 0x02, 0x03},
++#endif
++	{0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05},
++};
++
++/* ABE parameters */
++struct dpll_param abe_dpll_param[7] = {
++	/* 12M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 13M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 16.8M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 19.2M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 26M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 27M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 38.4M values */
++#ifdef CONFIG_OMAP4_SDC
++	{0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0},
++#else
++	{0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0},
++#endif
++};
++
++/* USB parameters */
++struct dpll_param usb_dpll_param[7] = {
++	/* 12M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 13M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 16.8M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 19.2M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 26M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 27M values */
++	{0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0},
++	/* 38.4M values */
++#ifdef CONFIG_OMAP4_SDC
++	{0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
++#else
++	{0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0},
++#endif
++};
++
++typedef struct dpll_param dpll_param;
++
++static void configure_mpu_dpll(u32 clk_index)
++{
++	dpll_param *dpll_param_p;
++
++	/* Unlock the MPU dpll */
++	sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS);
++	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY);
++
++	/* Program MPU DPLL */
++	dpll_param_p = &mpu_dpll_param[clk_index];
++
++	sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); /* Disable DPLL autoidle */
++
++	/* Set M,N,M2 values */
++	sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m);
++	sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n);
++	sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2);
++	sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1);
++
++	/* Lock the mpu dpll */
++	sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10);
++	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY);
++
++	return;
++}
++
++static void configure_iva_dpll(u32 clk_index)
++{
++	dpll_param *dpll_param_p;
++
++	/* Unlock the IVA dpll */
++	sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS);
++	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY);
++
++	/* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */
++	sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1);
++
++	/* Program IVA DPLL */
++	dpll_param_p = &iva_dpll_param[clk_index];
++
++	sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); /* Disable DPLL autoidle */
++
++	/* Set M,N,M4,M5 */
++	sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m);
++	sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n);
++	sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4);
++	sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1);
++	sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5);
++	sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1);
++
++	/* Lock the iva dpll */
++	sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK);
++	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY);
++
++	return;
++}
++
++static void configure_per_dpll(u32 clk_index)
++{
++	dpll_param *dpll_param_p;
++
++	/* Unlock the PER dpll */
++	sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS);
++	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY);
++
++	/* Program PER DPLL */
++	dpll_param_p = &per_dpll_param[clk_index];
++
++	/* Disable autoidle */
++	sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0);
++
++	sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m);
++	sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n);
++	sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2);
++	sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3);
++	sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4);
++	sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5);
++	sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6);
++	sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7);
++
++//	if(omap_revision() == OMAP4430_ES1_0)
++//	{
++		/* Do this only on ES1.0 */
++		sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1);
++		sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1);
++		sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1);
++		sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1);
++		sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1);
++		sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1);
++//	}
++
++	/* Lock the per dpll */
++	sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK);
++	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY);
++
++	return;
++}
++
++static void configure_abe_dpll(u32 clk_index)
++{
++	dpll_param *dpll_param_p;
++
++	/* Select sys_clk as ref clk for ABE dpll */
++	sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0);
++
++	/* Enable slimbus and pad clocks */
++	sr32(CM_CLKSEL_ABE, 0, 32, 0x500);
++
++	/* Unlock the ABE dpll */
++	sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS);
++	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY);
++
++	/* Program ABE DPLL */
++	dpll_param_p = &abe_dpll_param[clk_index];
++
++	/* Disable autoidle */
++	sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0);
++
++	sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m);
++	sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n);
++
++	/* Force DPLL CLKOUTHIF to stay enabled */
++	sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500);
++	sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2);
++	sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1);
++	/* Force DPLL CLKOUTHIF to stay enabled */
++	sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100);
++	sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3);
++	sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1);
++
++	/* Lock the abe dpll */
++	sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK);
++	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY);
++
++	return;
++}
++
++static void configure_usb_dpll(u32 clk_index)
++{
++	dpll_param *dpll_param_p;
++
++	/* Select the 60Mhz clock 480/8 = 60*/
++	sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1);
++
++	/* Unlock the USB dpll */
++	sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS);
++	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY);
++
++	/* Program USB DPLL */
++	dpll_param_p = &usb_dpll_param[clk_index];
++
++	/* Disable autoidle */
++	sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0);
++
++	sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m);
++	sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n);
++
++	/* Force DPLL CLKOUT to stay active */
++	sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100);
++	sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2);
++	sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1);
++	sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1);
++
++	/* Lock the usb dpll */
++	sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK);
++	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY);
++
++	/* force enable the CLKDCOLDO clock */
++	sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100);
++
++	return;
++}
++
++static void configure_core_dpll(clk_index)
++{
++	dpll_param *dpll_param_p;
++
++	/* Get the sysclk speed from cm_sys_clksel
++	 * Set it to 38.4 MHz, in case ROM code is bypassed
++	 */
++	if (!clk_index)
++		return;
++
++	/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
++	sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
++
++	/* Unlock the CORE dpll */
++	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
++	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
++
++	/* Program Core DPLL */
++	if(omap_revision() == OMAP4430_ES1_0)
++		dpll_param_p = &core_dpll_param_l3_190[clk_index];
++	else if(omap_revision() == OMAP4430_ES2_0)
++		dpll_param_p = &core_dpll_param[clk_index];
++	else if(omap_revision() == OMAP4430_ES2_1)
++		dpll_param_p = &core_dpll_param_ddr400[clk_index];
++
++	/* Disable autoidle */
++	sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
++
++	sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
++	sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
++	sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
++	sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
++	sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
++	sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
++	sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
++	sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
++
++	if(omap_revision() == OMAP4430_ES1_0)
++	{
++		/* Do this only on ES1.0 */
++		sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
++	}
++
++
++	/* Lock the core dpll */
++	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
++	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
++
++	return;
++}
++
++
++void configure_core_dpll_no_lock(void)
++{
++	dpll_param *dpll_param_p;
++	u32 clk_index;
++
++	/* Get the sysclk speed from cm_sys_clksel
++	 * Set it to 38.4 MHz, in case ROM code is bypassed
++	 */
++	__raw_writel(0x7,CM_SYS_CLKSEL);
++	clk_index = 7;
++
++	clk_index = clk_index - 1;
++	/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
++	sr32(CM_CLKSEL_CORE, 0, 32, 0x110);
++
++	/* Unlock the CORE dpll */
++	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS);
++	wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY);
++
++	/* Program Core DPLL */
++	if(omap_revision() == OMAP4430_ES1_0)
++		dpll_param_p = &core_dpll_param_l3_190[clk_index];
++	else if(omap_revision() == OMAP4430_ES2_0)
++		dpll_param_p = &core_dpll_param[clk_index];
++	else if(omap_revision() == OMAP4430_ES2_1)
++		dpll_param_p = &core_dpll_param_ddr400[clk_index];
++
++	/* Disable autoidle */
++	sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0);
++
++	sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m);
++	sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n);
++	sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2);
++	sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3);
++	sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4);
++	sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5);
++	sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6);
++	sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7);
++
++//	if(omap_revision() == OMAP4430_ES1_0)
++//	{
++		/* Do this only on ES1.0 */
++		sr32(CM_DIV_M2_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M3_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M4_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M5_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M6_DPLL_CORE, 8, 1, 0x1);
++		sr32(CM_DIV_M7_DPLL_CORE, 8, 1, 0x1);
++//	}
++
++	return;
++}
++
++void lock_core_dpll(void)
++{
++	/* Lock the core dpll */
++	sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK);
++	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
++
++	return;
++}
++
++void lock_core_dpll_shadow(void)
++{
++	dpll_param *dpll_param_p;
++	/* Lock the core dpll using freq update method */
++	*(volatile int*)0x4A004120 = 10;	//(CM_CLKMODE_DPLL_CORE)
++
++	if(omap_revision() == OMAP4430_ES1_0)
++		dpll_param_p = &core_dpll_param_l3_190[6];
++	else if(omap_revision() == OMAP4430_ES2_0)
++		dpll_param_p = &core_dpll_param[6];
++	else if(omap_revision() == OMAP4430_ES2_1)
++		dpll_param_p = &core_dpll_param_ddr400[6];
++
++	/* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1,
++	 * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1
++	 */
++	*(volatile int*)0x4A004260 = 0x70D | (dpll_param_p->m2 << 11);
++
++	/* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */
++	while( ( (*(volatile int*)0x4A004260) & 0x1) == 0x1 );
++
++	/* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */
++	wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY);
++	//lock_core_dpll();
++
++	return;
++}
++
++static void enable_all_clocks(void)
++{
++	volatile int regvalue = 0;
++
++	/* Enable Ducati clocks */
++	sr32(CM_DUCATI_DUCATI_CLKCTRL, 0, 32, 0x1);
++	sr32(CM_DUCATI_CLKSTCTRL, 0, 32, 0x2);
++
++	wait_on_value(BIT8, BIT8, CM_DUCATI_CLKSTCTRL, LDELAY);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_DUCATI_DUCATI_CLKCTRL, LDELAY);
++
++	/* Enable ivahd and sl2 clocks */
++	sr32(IVAHD_IVAHD_CLKCTRL, 0, 32, 0x1);
++	sr32(IVAHD_SL2_CLKCTRL, 0, 32, 0x1);
++	sr32(IVAHD_CLKSTCTRL, 0, 32, 0x2);
++
++	wait_on_value(BIT8, BIT8, IVAHD_CLKSTCTRL, LDELAY);
++
++	/* wait for ivahd to become accessible */
++	//wait_on_value(BIT18|BIT17|BIT16, 0, IVAHD_IVAHD_CLKCTRL, LDELAY);
++	/* wait for sl2 to become accessible */
++	//wait_on_value(BIT17|BIT16, 0, IVAHD_SL2_CLKCTRL, LDELAY);
++
++	/* Enable Tesla clocks */
++	sr32(DSP_DSP_CLKCTRL, 0, 32, 0x1);
++	sr32(DSP_CLKSTCTRL, 0, 32, 0x2);
++
++	wait_on_value(BIT8, BIT8, DSP_CLKSTCTRL, LDELAY);
++
++	/* wait for tesla to become accessible */
++	//wait_on_value(BIT18|BIT17|BIT16, 0, DSP_DSP_CLKCTRL, LDELAY);
++
++	/* TODO: Some hack needed by MM: Clean this */
++	#if 0 /* Doesn't work on some Zebu */
++	*(volatile int*)0x4a306910 = 0x00000003;
++	*(volatile int*)0x550809a0 = 0x00000001;
++	*(volatile int*)0x55080a20 = 0x00000007;
++	#endif
++
++	/* ABE clocks */
++	sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x3);
++	sr32(CM1_ABE_AESS_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM1_ABE_AESS_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_PDM_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_PDM_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_DMIC_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_DMIC_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_MCASP_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCASP_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_MCBSP1_CLKCTRL, 0, 32, 0x08000002);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP1_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_MCBSP2_CLKCTRL, 0, 32, 0x08000002);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP2_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_MCBSP3_CLKCTRL, 0, 32, 0x08000002);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_MCBSP3_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_SLIMBUS_CLKCTRL, 0, 32, 0xf02);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_SLIMBUS_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_TIMER5_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER5_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_TIMER6_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER6_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_TIMER7_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER7_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_TIMER8_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_TIMER8_CLKCTRL, LDELAY);
++	sr32(CM1_ABE_WDT3_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT17|BIT16, 0, CM1_ABE_WDT3_CLKCTRL, LDELAY);
++	/* Disable sleep transitions */
++	sr32(CM1_ABE_CLKSTCTRL, 0, 32, 0x0);
++
++	/* L4PER clocks */
++	sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2);
++	sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY);
++
++	/* GPIO clocks */
++	sr32(CM_L4PER_GPIO2_CLKCTRL, 0 ,32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY);
++
++	sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2);
++
++	/* I2C clocks */
++	sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY);
++
++	sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY);
++
++	/* MCSPI clocks */
++	sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY);
++
++	/* MMC clocks */
++	sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2);
++	sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY);
++	sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2);
++	sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY);
++
++	/* UART clocks */
++	sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY);
++	sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY);
++
++	/* WKUP clocks */
++	sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY);
++	sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002);
++	wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY);
++
++	sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY);
++
++	sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0);
++	sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3);
++	sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY);
++	sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY);
++	sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3);
++	sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY);
++	sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY);
++	sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY);
++	sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1);
++	wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY);
++
++	/* WDT clocks */
++	sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2);
++	wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY);
++
++	/* Enable Camera clocks */
++	sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x3);
++	sr32(CM_CAM_ISS_CLKCTRL, 0, 32, 0x102);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_ISS_CLKCTRL, LDELAY);
++	sr32(CM_CAM_FDIF_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_CAM_FDIF_CLKCTRL, LDELAY);
++	sr32(CM_CAM_CLKSTCTRL, 0, 32, 0x0);
++
++	/* Enable DSS clocks */
++	/* PM_DSS_PWRSTCTRL ON State and LogicState = 1 (Retention) */
++	*(volatile int*)0x4A307100 = 0x7; //DSS_PRM
++	sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x2);
++	sr32(CM_DSS_DSS_CLKCTRL, 0, 32, 0xf02);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DSS_CLKCTRL, LDELAY);
++	sr32(CM_DSS_DEISS_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_DSS_DEISS_CLKCTRL, LDELAY);
++	/* Check for DSS Clocks */
++	while (((*(volatile int*)0x4A009100) & 0xF00) != 0xE00)
++	/* Set HW_AUTO transition mode */
++	sr32(CM_DSS_CLKSTCTRL, 0, 32, 0x3);
++
++	/* Enable SGX clocks */
++	sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x2);
++	sr32(CM_SGX_SGX_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_SGX_SGX_CLKCTRL, LDELAY);
++	/* Check for SGX FCLK and ICLK */
++	while ( (*(volatile int*)0x4A009200) != 0x302 );
++	//sr32(CM_SGX_CLKSTCTRL, 0, 32, 0x0);
++	/* Enable hsi/unipro/usb clocks */
++	sr32(CM_L3INIT_HSI_CLKCTRL, 0, 32, 0x1);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSI_CLKCTRL, LDELAY);
++	sr32(CM_L3INIT_UNIPRO1_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_UNIPRO1_CLKCTRL, LDELAY);
++	sr32(CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBHOST_CLKCTRL, LDELAY);
++	sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSUSBOTG_CLKCTRL, LDELAY);
++	sr32(CM_L3INIT_HSUSBTLL_CLKCTRL, 0, 32, 0x1);
++	//wait_on_value(BIT17|BIT16, 0, CM_L3INIT_HSUSBTLL_CLKCTRL, LDELAY);
++	sr32(CM_L3INIT_FSUSB_CLKCTRL, 0, 32, 0x2);
++	//wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_FSUSB_CLKCTRL, LDELAY);
++	/* enable the 32K, 48M optional clocks and enable the module */
++	sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301);
++	//wait_on_value(BIT17|BIT16, 0, CM_L3INIT_USBPHY_CLKCTRL, LDELAY);
++	return;
++}
++
++/******************************************************************************
++ * prcm_init() - inits clocks for PRCM as defined in clocks.h
++ *   -- called from SRAM, or Flash (using temp SRAM stack).
++ *****************************************************************************/
++void prcm_init(void)
++{
++	u32 clk_index;
++
++	/* Get the sysclk speed from cm_sys_clksel
++	 * Set the CM_SYS_CLKSEL in case ROM code has not set
++	 */
++	__raw_writel(0x7,CM_SYS_CLKSEL);
++	clk_index = readl(CM_SYS_CLKSEL);
++	if (!clk_index)
++		return; /* Sys clk uninitialized */
++	/* Core DPLL is locked using FREQ update method */
++	/* configure_core_dpll(clk_index - 1); */
++
++	/* Configure all DPLL's at 100% OPP */
++	configure_mpu_dpll(clk_index - 1);
++	configure_iva_dpll(clk_index - 1);
++	configure_per_dpll(clk_index - 1);
++	configure_abe_dpll(clk_index - 1);
++	configure_usb_dpll(clk_index - 1);
++
++#ifdef CONFIG_OMAP4_SDC
++	/* Enable all clocks */
++	enable_all_clocks();
++#endif
++
++	return;
++}
+diff -uNr x-load-f243938.orig/board/omap4430panda/config.mk x-load-f243938/board/omap4430panda/config.mk
+--- x-load-f243938.orig/board/omap4430panda/config.mk	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/board/omap4430panda/config.mk	2012-06-07 14:45:39.445648666 -0300
+@@ -0,0 +1,21 @@
++#
++# (C) Copyright 2006-2009
++# Texas Instruments, <www.ti.com>
++#
++# SDP4430 board uses ARM-CortexA9 cpu
++# see http://www.ti.com/ for more information on Texas Instruments
++#
++# Physical Address:
++# 8000'0000 (bank0)
++# A000/0000 (bank1)
++# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
++# (mem base + reserved)
++
++# For use with external or internal boots.
++TEXT_BASE = 0x40304350
++
++
++# Handy to get symbols to debug ROM version.
++#TEXT_BASE = 0x0
++#TEXT_BASE = 0x08000000
++#TEXT_BASE = 0x04000000
+diff -uNr x-load-f243938.orig/board/omap4430panda/Makefile x-load-f243938/board/omap4430panda/Makefile
+--- x-load-f243938.orig/board/omap4430panda/Makefile	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/board/omap4430panda/Makefile	2012-06-07 14:45:39.445648666 -0300
+@@ -0,0 +1,49 @@
++#
++# (C) Copyright 2009
++# Texas Instruments, <www.ti.com>
++#
++# (C) Copyright 2000, 2001, 2002
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License
++# version 2 as published by the Free Software Foundation.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= lib$(BOARD).a
++
++OBJS	:= omap4430panda.o clock.o syslib.o
++SOBJS	:= platform.o
++
++$(LIB):	$(OBJS) $(SOBJS)
++	$(AR) crv $@ $^
++
++clean:
++	rm -f $(SOBJS) $(OBJS)
++
++distclean:	clean
++	rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
++		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
++
++-include .depend
++
++#########################################################################
+diff -uNr x-load-f243938.orig/board/omap4430panda/omap4430panda.c x-load-f243938/board/omap4430panda/omap4430panda.c
+--- x-load-f243938.orig/board/omap4430panda/omap4430panda.c	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/board/omap4430panda/omap4430panda.c	2012-06-07 14:45:39.445648666 -0300
+@@ -0,0 +1,1235 @@
++/*
++ * (C) Copyright 2004-2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#include <common.h>
++#include <asm/arch/cpu.h>
++#include <asm/io.h>
++#include <asm/arch/bits.h>
++#include <asm/arch/mux.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/arch/sys_info.h>
++#include <asm/arch/clocks.h>
++#include <asm/arch/mem.h>
++#include <i2c.h>
++#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
++#include <linux/mtd/nand_legacy.h>
++#endif
++
++/* EMIF and DMM registers */
++#define EMIF1_BASE			0x4c000000
++#define EMIF2_BASE			0x4d000000
++#define DMM_BASE			0x4e000000
++/* EMIF */
++#define EMIF_MOD_ID_REV			0x0000
++#define EMIF_STATUS			0x0004
++#define EMIF_SDRAM_CONFIG		0x0008
++#define EMIF_LPDDR2_NVM_CONFIG		0x000C
++#define EMIF_SDRAM_REF_CTRL		0x0010
++#define EMIF_SDRAM_REF_CTRL_SHDW	0x0014
++#define EMIF_SDRAM_TIM_1		0x0018
++#define EMIF_SDRAM_TIM_1_SHDW		0x001C
++#define EMIF_SDRAM_TIM_2		0x0020
++#define EMIF_SDRAM_TIM_2_SHDW		0x0024
++#define EMIF_SDRAM_TIM_3		0x0028
++#define EMIF_SDRAM_TIM_3_SHDW		0x002C
++#define EMIF_LPDDR2_NVM_TIM		0x0030
++#define EMIF_LPDDR2_NVM_TIM_SHDW	0x0034
++#define EMIF_PWR_MGMT_CTRL		0x0038
++#define EMIF_PWR_MGMT_CTRL_SHDW		0x003C
++#define EMIF_LPDDR2_MODE_REG_DATA	0x0040
++#define EMIF_LPDDR2_MODE_REG_CFG	0x0050
++#define EMIF_L3_CONFIG			0x0054
++#define EMIF_L3_CFG_VAL_1		0x0058
++#define EMIF_L3_CFG_VAL_2		0x005C
++#define IODFT_TLGC			0x0060
++#define EMIF_PERF_CNT_1			0x0080
++#define EMIF_PERF_CNT_2			0x0084
++#define EMIF_PERF_CNT_CFG		0x0088
++#define EMIF_PERF_CNT_SEL		0x008C
++#define EMIF_PERF_CNT_TIM		0x0090
++#define EMIF_READ_IDLE_CTRL		0x0098
++#define EMIF_READ_IDLE_CTRL_SHDW	0x009c
++#define EMIF_ZQ_CONFIG			0x00C8
++#define EMIF_DDR_PHY_CTRL_1		0x00E4
++#define EMIF_DDR_PHY_CTRL_1_SHDW	0x00E8
++#define EMIF_DDR_PHY_CTRL_2		0x00EC
++
++#define DMM_LISA_MAP_0 			0x0040
++#define DMM_LISA_MAP_1 			0x0044
++#define DMM_LISA_MAP_2 			0x0048
++#define DMM_LISA_MAP_3 			0x004C
++
++#define MR0_ADDR			0
++#define MR1_ADDR			1
++#define MR2_ADDR			2
++#define MR4_ADDR			4
++#define MR10_ADDR			10
++#define MR16_ADDR			16
++#define REF_EN				0x40000000
++/* defines for MR1 */
++#define MR1_BL4				2
++#define MR1_BL8				3
++#define MR1_BL16			4
++
++#define MR1_BT_SEQ			0
++#define BT_INT				1
++
++#define MR1_WC				0
++#define MR1_NWC				1
++
++#define MR1_NWR3			1
++#define MR1_NWR4			2
++#define MR1_NWR5			3
++#define MR1_NWR6			4
++#define MR1_NWR7			5
++#define MR1_NWR8			6
++
++#define MR1_VALUE	(MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3)  \
++							| (MR1_BL8 << 0)
++
++/* defines for MR2 */
++#define MR2_RL3_WL1			1
++#define MR2_RL4_WL2			2
++#define MR2_RL5_WL2			3
++#define MR2_RL6_WL3			4
++
++/* defines for MR10 */
++#define MR10_ZQINIT			0xFF
++#define MR10_ZQRESET			0xC3
++#define MR10_ZQCL			0xAB
++#define MR10_ZQCS			0x56
++
++
++/* TODO: FREQ update method is not working so shadow registers programming
++ * is just for same of completeness. This would be safer if auto
++ * trasnitions are working
++ */
++#define FREQ_UPDATE_EMIF
++/* EMIF Needs to be configured@19.2 MHz and shadow registers
++ * should be programmed for new OPP.
++ */
++/* Elpida 2x2Gbit */
++#define SDRAM_CONFIG_INIT		0x80800EB1
++#define DDR_PHY_CTRL_1_INIT		0x849FFFF5
++#define READ_IDLE_CTRL			0x000501FF
++#define PWR_MGMT_CTRL			0x4000000f
++#define PWR_MGMT_CTRL_OPP100		0x4000000f
++#define ZQ_CONFIG			0x500b3215
++
++#define CS1_MR(mr)	((mr) | 0x80000000)
++struct ddr_regs{
++	u32 tim1;
++	u32 tim2;
++	u32 tim3;
++	u32 phy_ctrl_1;
++	u32 ref_ctrl;
++	u32 config_init;
++	u32 config_final;
++	u32 zq_config;
++	u8 mr1;
++	u8 mr2;
++};
++const struct ddr_regs ddr_regs_380_mhz = {
++	.tim1		= 0x10cb061a,
++	.tim2		= 0x20350d52,
++	.tim3		= 0x00b1431f,
++	.phy_ctrl_1	= 0x849FF408,
++	.ref_ctrl	= 0x000005ca,
++	.config_init	= 0x80000eb1,
++	.config_final	= 0x80001ab1,
++	.zq_config	= 0x500b3215,
++	.mr1		= 0x83,
++	.mr2		= 0x4
++};
++
++/*
++ * Unused timings - but we may need them later
++ * Keep them commented
++ */
++#if 0
++const struct ddr_regs ddr_regs_400_mhz = {
++	.tim1		= 0x10eb065a,
++	.tim2		= 0x20370dd2,
++	.tim3		= 0x00b1c33f,
++	.phy_ctrl_1	= 0x849FF408,
++	.ref_ctrl	= 0x00000618,
++	.config_init	= 0x80000eb1,
++	.config_final	= 0x80001ab1,
++	.zq_config	= 0x500b3215,
++	.mr1		= 0x83,
++	.mr2		= 0x4
++};
++
++const struct ddr_regs ddr_regs_200_mhz = {
++	.tim1		= 0x08648309,
++	.tim2		= 0x101b06ca,
++	.tim3		= 0x0048a19f,
++	.phy_ctrl_1	= 0x849FF405,
++	.ref_ctrl	= 0x0000030c,
++	.config_init	= 0x80000eb1,
++	.config_final	= 0x80000eb1,
++	.zq_config	= 0x500b3215,
++	.mr1		= 0x23,
++	.mr2		= 0x1
++};
++#endif
++
++const struct ddr_regs ddr_regs_200_mhz_2cs = {
++	.tim1		= 0x08648309,
++	.tim2		= 0x101b06ca,
++	.tim3		= 0x0048a19f,
++	.phy_ctrl_1	= 0x849FF405,
++	.ref_ctrl	= 0x0000030c,
++	.config_init	= 0x80000eb9,
++	.config_final	= 0x80000eb9,
++	.zq_config	= 0xD00b3215,
++	.mr1		= 0x23,
++	.mr2		= 0x1
++};
++
++const struct ddr_regs ddr_regs_400_mhz_2cs = {
++	/* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
++	.tim1		= 0x10eb0662,
++	.tim2		= 0x20370dd2,
++	.tim3		= 0x00b1c33f,
++	.phy_ctrl_1	= 0x849FF408,
++	.ref_ctrl	= 0x00000618,
++	.config_init	= 0x80000eb9,
++	.config_final	= 0x80001ab9,
++	.zq_config	= 0xD00b3215,
++	.mr1		= 0x83,
++	.mr2		= 0x4
++};
++
++/*******************************************************
++ * Routine: delay
++ * Description: spinning delay to use before udelay works
++ ******************************************************/
++static inline void delay(unsigned long loops)
++{
++	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
++			  "bne 1b" : "=r" (loops) : "0"(loops));
++}
++
++
++void big_delay(unsigned int count)
++{
++	int i;
++	for (i=0; i<count; i++)
++		delay(1);
++}
++
++/* TODO: FREQ update method is not working so shadow registers programming
++ * is just for same of completeness. This would be safer if auto
++ * trasnitions are working
++ */
++static int emif_config(unsigned int base)
++{
++	unsigned int reg_value, rev;
++	const struct ddr_regs *ddr_regs;
++	rev = omap_revision();
++
++	if(rev == OMAP4430_ES1_0)
++		ddr_regs = &ddr_regs_380_mhz;
++	else if (rev == OMAP4430_ES2_0)
++		ddr_regs = &ddr_regs_200_mhz_2cs;
++	else if (rev == OMAP4430_ES2_1)
++		ddr_regs = &ddr_regs_400_mhz_2cs;
++	/*
++	 * set SDRAM CONFIG register
++	 * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
++	 * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0
++	 * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3
++	 * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks
++	 * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0
++ 	 * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2  - 512- 9 column
++	 * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
++	 */
++	*(volatile int*)(base + EMIF_LPDDR2_NVM_CONFIG) &= 0xBFFFFFFF;
++	*(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_init;
++
++	/* PHY control values */
++	*(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = DDR_PHY_CTRL_1_INIT;
++	*(volatile int*)(base + EMIF_DDR_PHY_CTRL_1_SHDW)= ddr_regs->phy_ctrl_1;
++
++	/*
++	 * EMIF_READ_IDLE_CTRL
++	 */
++	*(volatile int*)(base + EMIF_READ_IDLE_CTRL) = READ_IDLE_CTRL;
++	*(volatile int*)(base + EMIF_READ_IDLE_CTRL_SHDW) = READ_IDLE_CTRL;
++
++	/*
++	 * EMIF_SDRAM_TIM_1
++	 */
++	*(volatile int*)(base + EMIF_SDRAM_TIM_1) = ddr_regs->tim1;
++	*(volatile int*)(base + EMIF_SDRAM_TIM_1_SHDW) = ddr_regs->tim1;
++
++	/*
++	 * EMIF_SDRAM_TIM_2
++	 */
++	*(volatile int*)(base + EMIF_SDRAM_TIM_2) = ddr_regs->tim2;
++	*(volatile int*)(base + EMIF_SDRAM_TIM_2_SHDW) = ddr_regs->tim2;
++
++	/*
++	 * EMIF_SDRAM_TIM_3
++	 */
++	*(volatile int*)(base + EMIF_SDRAM_TIM_3) = ddr_regs->tim3;
++	*(volatile int*)(base + EMIF_SDRAM_TIM_3_SHDW) = ddr_regs->tim3;
++
++	*(volatile int*)(base + EMIF_ZQ_CONFIG) = ddr_regs->zq_config;
++	/*
++	 * EMIF_PWR_MGMT_CTRL
++	 */
++	//*(volatile int*)(base + EMIF_PWR_MGMT_CTRL) = PWR_MGMT_CTRL;
++	//*(volatile int*)(base + EMIF_PWR_MGMT_CTRL_SHDW) = PWR_MGMT_CTRL_OPP100;
++	/*
++	 * poll MR0 register (DAI bit)
++	 * REG_CS[31] = 0 -- Mode register command to CS0
++	 * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
++	 * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
++	 */
++
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = MR0_ADDR;
++	do {
++		reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
++	} while ((reg_value & 0x1) != 0);
++
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR0_ADDR);
++	do {
++		reg_value = *(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA);
++	} while ((reg_value & 0x1) != 0);
++
++
++	/* set MR10 register */
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR10_ADDR;
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT;
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR10_ADDR);
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = MR10_ZQINIT;
++
++	/* wait for tZQINIT=1us  */
++	delay(10);
++
++	/* set MR1 register */
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR1_ADDR;
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1;
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR1_ADDR);
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr1;
++
++
++	/* set MR2 register RL=6 for OPP100 */
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR2_ADDR;
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2;
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) = CS1_MR(MR2_ADDR);
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = ddr_regs->mr2;
++
++	/* Set SDRAM CONFIG register again here with final RL-WL value */
++	*(volatile int*)(base + EMIF_SDRAM_CONFIG) = ddr_regs->config_final;
++	*(volatile int*)(base + EMIF_DDR_PHY_CTRL_1) = ddr_regs->phy_ctrl_1;
++
++	/*
++	 * EMIF_SDRAM_REF_CTRL
++	 * refresh rate = DDR_CLK / reg_refresh_rate
++	 * 3.9 uS = (400MHz)	/ reg_refresh_rate
++	 */
++	*(volatile int*)(base + EMIF_SDRAM_REF_CTRL) = ddr_regs->ref_ctrl;
++	*(volatile int*)(base + EMIF_SDRAM_REF_CTRL_SHDW) = ddr_regs->ref_ctrl;
++
++	/* set MR16 register */
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG)= MR16_ADDR | REF_EN;
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0;
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_CFG) =
++						 CS1_MR(MR16_ADDR | REF_EN);
++	*(volatile int*)(base + EMIF_LPDDR2_MODE_REG_DATA) = 0;
++	/* LPDDR2 init complete */
++
++}
++/*****************************************
++ * Routine: ddr_init
++ * Description: Configure DDR
++ * EMIF1 -- CS0 -- DDR1 (256 MB)
++ * EMIF2 -- CS0 -- DDR2 (256 MB)
++ *****************************************/
++static void ddr_init(void)
++{
++	unsigned int base_addr, rev;
++	rev = omap_revision();
++
++	if (rev == OMAP4430_ES1_0)
++	{
++		/* Configurte the Control Module DDRIO device */
++		__raw_writel(0x1c1c1c1c, 0x4A100638);
++		__raw_writel(0x1c1c1c1c, 0x4A10063c);
++		__raw_writel(0x1c1c1c1c, 0x4A100640);
++		__raw_writel(0x1c1c1c1c, 0x4A100648);
++		__raw_writel(0x1c1c1c1c, 0x4A10064c);
++		__raw_writel(0x1c1c1c1c, 0x4A100650);
++		/* LPDDR2IO set to NMOS PTV */
++		__raw_writel(0x00ffc000, 0x4A100704);
++	} else if (rev == OMAP4430_ES2_0) {
++		__raw_writel(0x9e9e9e9e, 0x4A100638);
++		__raw_writel(0x9e9e9e9e, 0x4A10063c);
++		__raw_writel(0x9e9e9e9e, 0x4A100640);
++		__raw_writel(0x9e9e9e9e, 0x4A100648);
++		__raw_writel(0x9e9e9e9e, 0x4A10064c);
++		__raw_writel(0x9e9e9e9e, 0x4A100650);
++		/* LPDDR2IO set to NMOS PTV */
++		__raw_writel(0x00ffc000, 0x4A100704);
++	}
++
++	/*
++	 * DMM Configuration
++	 */
++
++	/* Both EMIFs 128 byte interleaved*/
++	if (rev == OMAP4430_ES1_0)
++		*(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80540300;
++	else
++		*(volatile int*)(DMM_BASE + DMM_LISA_MAP_0) = 0x80640300;
++
++	/* EMIF2 only at 0x90000000 */
++	//*(volatile int*)(DMM_BASE + DMM_LISA_MAP_1) = 0x90400200;
++
++	*(volatile int*)(DMM_BASE + DMM_LISA_MAP_2) = 0x00000000;
++	*(volatile int*)(DMM_BASE + DMM_LISA_MAP_3) = 0xFF020100;
++
++	/* DDR needs to be initialised @ 19.2 MHz
++	 * So put core DPLL in bypass mode
++	 * Configure the Core DPLL but don't lock it
++	 */
++	configure_core_dpll_no_lock();
++
++	/* No IDLE: BUG in SDC */
++	//sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
++	//while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
++	*(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
++	*(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x0;
++
++	base_addr = EMIF1_BASE;
++	emif_config(base_addr);
++
++	/* Configure EMIF24D */
++	base_addr = EMIF2_BASE;
++	emif_config(base_addr);
++	/* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
++	lock_core_dpll_shadow();
++	/* TODO: SDC needs few hacks to get DDR freq update working */
++
++	/* Set DLL_OVERRIDE = 0 */
++	*(volatile int*)CM_DLL_CTRL = 0x0;
++
++	delay(200);
++
++	/* Check for DDR PHY ready for EMIF1 & EMIF2 */
++	while((((*(volatile int*)(EMIF1_BASE + EMIF_STATUS))&(0x04)) != 0x04) \
++	|| (((*(volatile int*)(EMIF2_BASE + EMIF_STATUS))&(0x04)) != 0x04));
++
++	/* Reprogram the DDR PYHY Control register */
++	/* PHY control values */
++
++	sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
++        sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
++
++	/* Put the Core Subsystem PD to ON State */
++
++	/* No IDLE: BUG in SDC */
++	//sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
++	//while(((*(volatile int*)CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700);
++	*(volatile int*)(EMIF1_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
++	*(volatile int*)(EMIF2_BASE + EMIF_PWR_MGMT_CTRL) = 0x80000000;
++
++	/* SYSTEM BUG:
++	 * In n a specific situation, the OCP interface between the DMM and
++	 * EMIF may hang.
++	 * 1. A TILER port is used to perform 2D burst writes of
++	 * 	 width 1 and height 8
++	 * 2. ELLAn port is used to perform reads
++	 * 3. All accesses are routed to the same EMIF controller
++	 *
++	 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
++	 * be kept higher than default 0x7. As per recommondation 0x0A will
++	 * be used for better performance with REG_LL_THRESH_MAX = 0x00
++	 */
++	if (rev == OMAP4430_ES1_0) {
++		*(volatile int*)(EMIF1_BASE + EMIF_L3_CONFIG) = 0x0A0000FF;
++		*(volatile int*)(EMIF2_BASE + EMIF_L3_CONFIG) = 0x0A0000FF;
++	}
++
++	/*
++	 * DMM : DMM_LISA_MAP_0(Section_0)
++	 * [31:24] SYS_ADDR 		0x80
++	 * [22:20] SYS_SIZE		0x7 - 2Gb
++	 * [19:18] SDRC_INTLDMM		0x1 - 128 byte
++	 * [17:16] SDRC_ADDRSPC 	0x0
++	 * [9:8] SDRC_MAP 		0x3
++	 * [7:0] SDRC_ADDR		0X0
++	 */
++	reset_phy(EMIF1_BASE);
++	reset_phy(EMIF2_BASE);
++
++	*((volatile int *)0x80000000) = 0;
++	*((volatile int *)0x80000080) = 0;
++	//*((volatile int *)0x90000000) = 0;
++}
++/*****************************************
++ * Routine: board_init
++ * Description: Early hardware init.
++ *****************************************/
++int board_init(void)
++{
++	return 0;
++}
++
++/*************************************************************
++ * Routine: get_mem_type(void) - returns the kind of memory connected
++ * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
++ *************************************************************/
++u32 get_mem_type(void)
++{
++	/* no nand, so return GPMC_NONE */
++	return GPMC_NONE;	
++}
++
++/*****************************************
++ * Routine: secure_unlock
++ * Description: Setup security registers for access
++ * (GP Device only)
++ *****************************************/
++void secure_unlock_mem(void)
++{
++	/* Permission values for registers -Full fledged permissions to all */
++	#define UNLOCK_1 0xFFFFFFFF
++	#define UNLOCK_2 0x00000000
++	#define UNLOCK_3 0x0000FFFF
++
++	/* Protection Module Register Target APE (PM_RT)*/
++	__raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
++	__raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
++	__raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
++	__raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
++
++	__raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
++	__raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
++	__raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
++
++	__raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
++	__raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
++	__raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
++	__raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
++
++	/* IVA Changes */
++	__raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
++	__raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
++	__raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
++
++	__raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
++}
++
++/**********************************************************
++ * Routine: try_unlock_sram()
++ * Description: If chip is GP/EMU(special) type, unlock the SRAM for
++ *  general use.
++ ***********************************************************/
++void try_unlock_memory(void)
++{
++	int mode;
++
++	/* if GP device unlock device SRAM for general use */
++	/* secure code breaks for Secure/Emulation device - HS/E/T*/
++	return;
++}
++
++
++#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
++static scale_vcores(void)
++{
++	unsigned int rev = omap_revision();
++	/* For VC bypass only VCOREx_CGF_FORCE  is necessary and
++	 * VCOREx_CFG_VOLTAGE  changes can be discarded
++	 */
++	/* PRM_VC_CFG_I2C_MODE */
++	*(volatile int*)(0x4A307BA8) = 0x0;
++	/* PRM_VC_CFG_I2C_CLK */
++	*(volatile int*)(0x4A307BAC) = 0x6026;
++
++	/* set VCORE1 force VSEL */
++	/* PRM_VC_VAL_BYPASS) */
++	if(rev == OMAP4430_ES1_0)
++		*(volatile int*)(0x4A307BA0) = 0x3B5512;
++	else
++		*(volatile int*)(0x4A307BA0) = 0x3A5512;
++
++	*(volatile int*)(0x4A307BA0) |= 0x1000000;
++	while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
++
++	/* PRM_IRQSTATUS_MPU */
++	*(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010);
++
++
++	/* FIXME: set VCORE2 force VSEL, Check the reset value */
++	/* PRM_VC_VAL_BYPASS) */
++        if(rev == OMAP4430_ES1_0)
++		*(volatile int*)(0x4A307BA0) = 0x315B12;
++	else
++		*(volatile int*)(0x4A307BA0) = 0x295B12;
++	*(volatile int*)(0x4A307BA0) |= 0x1000000;
++	while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
++
++	/* PRM_IRQSTATUS_MPU */
++	*(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010);
++
++	/*/set VCORE3 force VSEL */
++	/* PRM_VC_VAL_BYPASS */
++	if(rev == OMAP4430_ES1_0)
++		*(volatile int*)(0x4A307BA0) = 0x316112;
++	else if (rev == OMAP4430_ES2_0)
++		*(volatile int*)(0x4A307BA0) = 0x296112;
++	else if (rev == OMAP4430_ES2_1)
++		*(volatile int*)(0x4A307BA0) = 0x2A6112;
++	*(volatile int*)(0x4A307BA0) |= 0x1000000;
++	while((*(volatile int*)(0x4A307BA0)) & 0x1000000);
++
++	/* PRM_IRQSTATUS_MPU */
++	*(volatile int*)(0x4A306010) = *(volatile int*)(0x4A306010);
++
++}
++#endif
++
++/**********************************************************
++ * Routine: s_init
++ * Description: Does early system init of muxing and clocks.
++ * - Called path is with SRAM stack.
++ **********************************************************/
++
++void s_init(void)
++{
++	unsigned int rev = omap_revision();
++
++	set_muxconf_regs();
++	delay(100);
++
++	/* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */
++	/* Currently SMI in Kernel on ES2 devices seems to have an isse
++	 * Once that is resolved, we can postpone this config to kernel
++	 */
++	//setup_auxcr(get_device_type(), external_boot);
++
++	ddr_init();
++
++/* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
++#if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
++	scale_vcores();
++#endif	
++	prcm_init();
++
++	if(rev != OMAP4430_ES1_0) {
++		if (__raw_readl(0x4805D138) & (1<<22)) {
++			sr32(0x4A30a31C, 8, 1, 0x1);  /* enable software ioreq */
++			sr32(0x4A30a31C, 1, 2, 0x0);  /* set for sys_clk (38.4MHz) */
++			sr32(0x4A30a31C, 16, 4, 0x1); /* set divisor to 2 */
++			sr32(0x4A30a110, 0, 1, 0x1);  /* set the clock source to active */
++			sr32(0x4A30a110, 2, 2, 0x3);  /* enable clocks */
++		}
++		else {
++			sr32(0x4A30a314, 8, 1, 0x1); /* enable software ioreq */
++			sr32(0x4A30a314, 1, 2, 0x2); /* set for PER_DPLL */
++			sr32(0x4A30a314, 16, 4, 0xf); /* set divisor to 16 */
++			sr32(0x4A30a110, 0, 1, 0x1); /* set the clock source to active */
++			sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */
++		}
++	}
++
++}
++
++/*******************************************************
++ * Routine: misc_init_r
++ * Description: Init ethernet (done here so udelay works)
++ ********************************************************/
++int misc_init_r(void)
++{
++	return 0;
++}
++
++/******************************************************
++ * Routine: wait_for_command_complete
++ * Description: Wait for posting to finish on watchdog
++ ******************************************************/
++void wait_for_command_complete(unsigned int wd_base)
++{
++	int pending = 1;
++	do {
++		pending = __raw_readl(wd_base + WWPS);
++	} while (pending);
++}
++
++/*******************************************************************
++ * Routine:ether_init
++ * Description: take the Ethernet controller out of reset and wait
++ *  		   for the EEPROM load to complete.
++ ******************************************************************/
++
++/**********************************************
++ * Routine: dram_init
++ * Description: sets uboots idea of sdram size
++ **********************************************/
++int dram_init(void)
++{
++	return 0;
++}
++
++#define		OMAP44XX_WKUP_CTRL_BASE		0x4A31E000 
++#if 1
++#define M0_SAFE M0
++#define M1_SAFE M1
++#define M2_SAFE M2
++#define M4_SAFE M4
++#define M7_SAFE M7
++#define M3_SAFE M3
++#define M5_SAFE M5
++#define M6_SAFE M6
++#else
++#define M0_SAFE M7
++#define M1_SAFE M7
++#define M2_SAFE M7
++#define M4_SAFE M7
++#define M7_SAFE M7
++#define M3_SAFE M7
++#define M5_SAFE M7
++#define M6_SAFE M7
++#endif
++#define		MV(OFFSET, VALUE)\
++			__raw_writew((VALUE), OMAP44XX_CTRL_BASE + (OFFSET));
++#define		MV1(OFFSET, VALUE)\
++			__raw_writew((VALUE), OMAP44XX_WKUP_CTRL_BASE + (OFFSET));
++
++#define		CP(x)	(CONTROL_PADCONF_##x)
++#define		WK(x)	(CONTROL_WKUP_##x)
++/*
++ * IEN  - Input Enable
++ * IDIS - Input Disable
++ * PTD  - Pull type Down
++ * PTU  - Pull type Up
++ * DIS  - Pull type selection is inactive
++ * EN   - Pull type selection is active
++ * M0   - Mode 0
++ * The commented string gives the final mux configuration for that pin
++ */
++
++#define MUX_DEFAULT_OMAP4() \
++	MV(CP(GPMC_AD0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_dat0 */ \
++	MV(CP(GPMC_AD1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_dat1 */ \
++	MV(CP(GPMC_AD2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_dat2 */ \
++	MV(CP(GPMC_AD3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_dat3 */ \
++	MV(CP(GPMC_AD4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_dat4 */ \
++	MV(CP(GPMC_AD5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_dat5 */ \
++	MV(CP(GPMC_AD6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_dat6 */ \
++	MV(CP(GPMC_AD7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_dat7 */ \
++	MV(CP(GPMC_AD8) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3))  /* gpio_32 */ \
++	MV(CP(GPMC_AD9) , ( PTU | IEN | M3))  /* gpio_33 */ \
++	MV(CP(GPMC_AD10) , ( PTU | IEN | M3))  /* gpio_34 */ \
++	MV(CP(GPMC_AD11) , ( PTU | IEN | M3))  /* gpio_35 */ \
++	MV(CP(GPMC_AD12) , ( PTU | IEN | M3))  /* gpio_36 */ \
++	MV(CP(GPMC_AD13) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3))  /* gpio_37 */ \
++	MV(CP(GPMC_AD14) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3))  /* gpio_38 */ \
++	MV(CP(GPMC_AD15) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3))  /* gpio_39 */ \
++	MV(CP(GPMC_A16) , ( M3))  /* gpio_40 */ \
++	MV(CP(GPMC_A17) , ( PTD | M3))  /* gpio_41 */ \
++	MV(CP(GPMC_A18) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_row6 */ \
++	MV(CP(GPMC_A19) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_row7 */ \
++	MV(CP(GPMC_A20) , ( IEN | M3))  /* gpio_44 */ \
++	MV(CP(GPMC_A21) , ( M3))  /* gpio_45 */ \
++	MV(CP(GPMC_A22) , ( M3))  /* gpio_46 */ \
++	MV(CP(GPMC_A23) , ( OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_col7 */ \
++	MV(CP(GPMC_A24) , ( PTD | M3))  /* gpio_48 */ \
++	MV(CP(GPMC_A25) , ( PTD | M3))  /* gpio_49 */ \
++	MV(CP(GPMC_NCS0) , ( M3))  /* gpio_50 */ \
++	MV(CP(GPMC_NCS1) , ( IEN | M3))  /* gpio_51 */ \
++	MV(CP(GPMC_NCS2) , ( IEN | M3))  /* gpio_52 */ \
++	MV(CP(GPMC_NCS3) , ( IEN | M3))  /* gpio_53 */ \
++	MV(CP(GPMC_NWP) , ( M3))  /* gpio_54 */ \
++	MV(CP(GPMC_CLK) , ( PTD | M3))  /* gpio_55 */ \
++	MV(CP(GPMC_NADV_ALE) , ( M3))  /* gpio_56 */ \
++	MV(CP(GPMC_NOE) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M1))  /* sdmmc2_clk */ \
++	MV(CP(GPMC_NWE) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* sdmmc2_cmd */ \
++	MV(CP(GPMC_NBE0_CLE) , ( M3))  /* gpio_59 */ \
++	MV(CP(GPMC_NBE1) , ( PTD | M3))  /* gpio_60 */ \
++	MV(CP(GPMC_WAIT0) , ( PTU | IEN | M3))  /* gpio_61 */ \
++	MV(CP(GPMC_WAIT1),	(PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_62 */ \
++	MV(CP(C2C_DATA11) , ( PTD | M3))  /* gpio_100 */ \
++	MV(CP(C2C_DATA12) , ( PTD | IEN | M3))  /* gpio_101 */ \
++	MV(CP(C2C_DATA13) , ( PTD | M3))  /* gpio_102 */ \
++	MV(CP(C2C_DATA14) , ( M1))  /* dsi2_te0 */ \
++	MV(CP(C2C_DATA15) , ( PTD | M3))  /* gpio_104 */ \
++	MV(CP(HDMI_HPD) , ( M0))  /* hdmi_hpd */ \
++	MV(CP(HDMI_CEC) , ( M0))  /* hdmi_cec */ \
++	MV(CP(HDMI_DDC_SCL) , ( PTU | M0))  /* hdmi_ddc_scl */ \
++	MV(CP(HDMI_DDC_SDA) , ( PTU | IEN | M0))  /* hdmi_ddc_sda */ \
++	MV(CP(CSI21_DX0) , ( IEN | M0))  /* csi21_dx0 */ \
++	MV(CP(CSI21_DY0) , ( IEN | M0))  /* csi21_dy0 */ \
++	MV(CP(CSI21_DX1) , ( IEN | M0))  /* csi21_dx1 */ \
++	MV(CP(CSI21_DY1) , ( IEN | M0))  /* csi21_dy1 */ \
++	MV(CP(CSI21_DX2) , ( IEN | M0))  /* csi21_dx2 */ \
++	MV(CP(CSI21_DY2) , ( IEN | M0))  /* csi21_dy2 */ \
++	MV(CP(CSI21_DX3) , ( PTD | M7))  /* csi21_dx3 */ \
++	MV(CP(CSI21_DY3) , ( PTD | M7))  /* csi21_dy3 */ \
++	MV(CP(CSI21_DX4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7))  /* csi21_dx4 */ \
++	MV(CP(CSI21_DY4) , ( PTD | OFF_EN | OFF_PD | OFF_IN | M7))  /* csi21_dy4 */ \
++	MV(CP(CSI22_DX0) , ( IEN | M0))  /* csi22_dx0 */ \
++	MV(CP(CSI22_DY0) , ( IEN | M0))  /* csi22_dy0 */ \
++	MV(CP(CSI22_DX1) , ( IEN | M0))  /* csi22_dx1 */ \
++	MV(CP(CSI22_DY1) , ( IEN | M0))  /* csi22_dy1 */ \
++	MV(CP(CAM_SHUTTER) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0))  /* cam_shutter */ \
++	MV(CP(CAM_STROBE) , ( OFF_EN | OFF_PD | OFF_OUT_PTD | M0))  /* cam_strobe */ \
++	MV(CP(CAM_GLOBALRESET) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3))  /* gpio_83 */ \
++	MV(CP(USBB1_ULPITLL_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_clk */ \
++	MV(CP(USBB1_ULPITLL_STP) , ( OFF_EN | OFF_OUT_PTD | M4))  /* usbb1_ulpiphy_stp */ \
++	MV(CP(USBB1_ULPITLL_DIR) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dir */ \
++	MV(CP(USBB1_ULPITLL_NXT) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_nxt */ \
++	MV(CP(USBB1_ULPITLL_DAT0) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dat0 */ \
++	MV(CP(USBB1_ULPITLL_DAT1) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dat1 */ \
++	MV(CP(USBB1_ULPITLL_DAT2) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dat2 */ \
++	MV(CP(USBB1_ULPITLL_DAT3) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dat3 */ \
++	MV(CP(USBB1_ULPITLL_DAT4) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dat4 */ \
++	MV(CP(USBB1_ULPITLL_DAT5) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dat5 */ \
++	MV(CP(USBB1_ULPITLL_DAT6) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dat6 */ \
++	MV(CP(USBB1_ULPITLL_DAT7) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M4))  /* usbb1_ulpiphy_dat7 */ \
++	MV(CP(USBB1_HSIC_DATA) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* usbb1_hsic_data */ \
++	MV(CP(USBB1_HSIC_STROBE) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* usbb1_hsic_strobe */ \
++	MV(CP(USBC1_ICUSB_DP) , ( IEN | M0))  /* usbc1_icusb_dp */ \
++	MV(CP(USBC1_ICUSB_DM) , ( IEN | M0))  /* usbc1_icusb_dm */ \
++	MV(CP(SDMMC1_CLK) , ( PTU | OFF_EN | OFF_OUT_PTD | M0))  /* sdmmc1_clk */ \
++	MV(CP(SDMMC1_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_cmd */ \
++	MV(CP(SDMMC1_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_dat0 */ \
++	MV(CP(SDMMC1_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_dat1 */ \
++	MV(CP(SDMMC1_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_dat2 */ \
++	MV(CP(SDMMC1_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_dat3 */ \
++	MV(CP(SDMMC1_DAT4) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_dat4 */ \
++	MV(CP(SDMMC1_DAT5) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_dat5 */ \
++	MV(CP(SDMMC1_DAT6) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_dat6 */ \
++	MV(CP(SDMMC1_DAT7) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc1_dat7 */ \
++	MV(CP(ABE_MCBSP2_CLKX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* abe_mcbsp2_clkx */ \
++	MV(CP(ABE_MCBSP2_DR) , ( IEN | OFF_EN | OFF_OUT_PTD | M0))  /* abe_mcbsp2_dr */ \
++	MV(CP(ABE_MCBSP2_DX) , ( OFF_EN | OFF_OUT_PTD | M0))  /* abe_mcbsp2_dx */ \
++	MV(CP(ABE_MCBSP2_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* abe_mcbsp2_fsx */ \
++	MV(CP(ABE_MCBSP1_CLKX) , ( IEN | M1))  /* abe_slimbus1_clock */ \
++	MV(CP(ABE_MCBSP1_DR) , ( IEN | M1))  /* abe_slimbus1_data */ \
++	MV(CP(ABE_MCBSP1_DX) , ( OFF_EN | OFF_OUT_PTD | M0))  /* abe_mcbsp1_dx */ \
++	MV(CP(ABE_MCBSP1_FSX) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* abe_mcbsp1_fsx */ \
++	MV(CP(ABE_PDM_UL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* abe_pdm_ul_data */ \
++	MV(CP(ABE_PDM_DL_DATA) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* abe_pdm_dl_data */ \
++	MV(CP(ABE_PDM_FRAME) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* abe_pdm_frame */ \
++	MV(CP(ABE_PDM_LB_CLK) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* abe_pdm_lb_clk */ \
++	MV(CP(ABE_CLKS) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* abe_clks */ \
++	MV(CP(ABE_DMIC_CLK1) , ( M0))  /* abe_dmic_clk1 */ \
++	MV(CP(ABE_DMIC_DIN1) , ( IEN | M0))  /* abe_dmic_din1 */ \
++	MV(CP(ABE_DMIC_DIN2) , ( IEN | M0))  /* abe_dmic_din2 */ \
++	MV(CP(ABE_DMIC_DIN3) , ( IEN | M0))  /* abe_dmic_din3 */ \
++	MV(CP(UART2_CTS) , ( PTU | IEN | M0))  /* uart2_cts */ \
++	MV(CP(UART2_RTS) , ( M0))  /* uart2_rts */ \
++	MV(CP(UART2_RX) , ( PTU | IEN | M0))  /* uart2_rx */ \
++	MV(CP(UART2_TX) , ( M0))  /* uart2_tx */ \
++	MV(CP(HDQ_SIO) , ( M3))  /* gpio_127 */ \
++	MV(CP(I2C1_SCL) , ( PTU | IEN | M0))  /* i2c1_scl */ \
++	MV(CP(I2C1_SDA) , ( PTU | IEN | M0))  /* i2c1_sda */ \
++	MV(CP(I2C2_SCL) , ( PTU | IEN | M0))  /* i2c2_scl */ \
++	MV(CP(I2C2_SDA) , ( PTU | IEN | M0))  /* i2c2_sda */ \
++	MV(CP(I2C3_SCL) , ( PTU | IEN | M0))  /* i2c3_scl */ \
++	MV(CP(I2C3_SDA) , ( PTU | IEN | M0))  /* i2c3_sda */ \
++	MV(CP(I2C4_SCL) , ( PTU | IEN | M0))  /* i2c4_scl */ \
++	MV(CP(I2C4_SDA) , ( PTU | IEN | M0))  /* i2c4_sda */ \
++	MV(CP(MCSPI1_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* mcspi1_clk */ \
++	MV(CP(MCSPI1_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* mcspi1_somi */ \
++	MV(CP(MCSPI1_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* mcspi1_simo */ \
++	MV(CP(MCSPI1_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* mcspi1_cs0 */ \
++	MV(CP(MCSPI1_CS1) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3))  /* mcspi1_cs1 */ \
++	MV(CP(MCSPI1_CS2) , ( PTU | OFF_EN | OFF_OUT_PTU | M3))  /* gpio_139 */ \
++	MV(CP(MCSPI1_CS3) , ( PTU | IEN | M3))  /* gpio_140 */ \
++	MV(CP(UART3_CTS_RCTX) , ( PTU | IEN | M0))  /* uart3_tx */ \
++	MV(CP(UART3_RTS_SD) , ( M0))  /* uart3_rts_sd */ \
++	MV(CP(UART3_RX_IRRX) , ( IEN | M0))  /* uart3_rx */ \
++	MV(CP(UART3_TX_IRTX) , ( M0))  /* uart3_tx */ \
++	MV(CP(SDMMC5_CLK) , ( PTU | IEN | OFF_EN | OFF_OUT_PTD | M0))  /* sdmmc5_clk */ \
++	MV(CP(SDMMC5_CMD) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc5_cmd */ \
++	MV(CP(SDMMC5_DAT0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc5_dat0 */ \
++	MV(CP(SDMMC5_DAT1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc5_dat1 */ \
++	MV(CP(SDMMC5_DAT2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc5_dat2 */ \
++	MV(CP(SDMMC5_DAT3) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* sdmmc5_dat3 */ \
++	MV(CP(MCSPI4_CLK) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* mcspi4_clk */ \
++	MV(CP(MCSPI4_SIMO) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* mcspi4_simo */ \
++	MV(CP(MCSPI4_SOMI) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* mcspi4_somi */ \
++	MV(CP(MCSPI4_CS0) , ( PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* mcspi4_cs0 */ \
++	MV(CP(UART4_RX) , ( IEN | M0))  /* uart4_rx */ \
++	MV(CP(UART4_TX) , ( M0))  /* uart4_tx */ \
++	MV(CP(USBB2_ULPITLL_CLK) , ( IEN | M3))  /* gpio_157 */ \
++	MV(CP(USBB2_ULPITLL_STP) , ( IEN | M5))  /* dispc2_data23 */ \
++	MV(CP(USBB2_ULPITLL_DIR) , ( IEN | M5))  /* dispc2_data22 */ \
++	MV(CP(USBB2_ULPITLL_NXT) , ( IEN | M5))  /* dispc2_data21 */ \
++	MV(CP(USBB2_ULPITLL_DAT0) , ( IEN | M5))  /* dispc2_data20 */ \
++	MV(CP(USBB2_ULPITLL_DAT1) , ( IEN | M5))  /* dispc2_data19 */ \
++	MV(CP(USBB2_ULPITLL_DAT2) , ( IEN | M5))  /* dispc2_data18 */ \
++	MV(CP(USBB2_ULPITLL_DAT3) , ( IEN | M5))  /* dispc2_data15 */ \
++	MV(CP(USBB2_ULPITLL_DAT4) , ( IEN | M5))  /* dispc2_data14 */ \
++	MV(CP(USBB2_ULPITLL_DAT5) , ( IEN | M5))  /* dispc2_data13 */ \
++	MV(CP(USBB2_ULPITLL_DAT6) , ( IEN | M5))  /* dispc2_data12 */ \
++	MV(CP(USBB2_ULPITLL_DAT7) , ( IEN | M5))  /* dispc2_data11 */ \
++	MV(CP(USBB2_HSIC_DATA) , ( PTD | OFF_EN | OFF_OUT_PTU | M3))  /* gpio_169 */ \
++	MV(CP(USBB2_HSIC_STROBE) , ( PTD | OFF_EN | OFF_OUT_PTU | M3))  /* gpio_170 */ \
++	MV(CP(UNIPRO_TX0) , ( PTD | IEN | M3))  /* gpio_171 */ \
++	MV(CP(UNIPRO_TY0) , ( OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_col1 */ \
++	MV(CP(UNIPRO_TX1) , ( OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_col2 */ \
++	MV(CP(UNIPRO_TY1) , ( OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_col3 */ \
++	MV(CP(UNIPRO_TX2) , ( PTU | IEN | M3))  /* gpio_0 */ \
++	MV(CP(UNIPRO_TY2) , ( PTU | IEN | M3))  /* gpio_1 */ \
++	MV(CP(UNIPRO_RX0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_row0 */ \
++	MV(CP(UNIPRO_RY0) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_row1 */ \
++	MV(CP(UNIPRO_RX1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_row2 */ \
++	MV(CP(UNIPRO_RY1) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_row3 */ \
++	MV(CP(UNIPRO_RX2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_row4 */ \
++	MV(CP(UNIPRO_RY2) , ( PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1))  /* kpd_row5 */ \
++	MV(CP(USBA0_OTG_CE) , ( PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0))  /* usba0_otg_ce */ \
++	MV(CP(USBA0_OTG_DP) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* usba0_otg_dp */ \
++	MV(CP(USBA0_OTG_DM) , ( IEN | OFF_EN | OFF_PD | OFF_IN | M0))  /* usba0_otg_dm */ \
++	MV(CP(FREF_CLK1_OUT) , ( M0))  /* fref_clk1_out */ \
++	MV(CP(FREF_CLK2_OUT) , ( PTD | IEN | M3))  /* gpio_182 */ \
++	MV(CP(SYS_NIRQ1) , ( PTU | IEN | M0))  /* sys_nirq1 */ \
++	MV(CP(SYS_NIRQ2) , ( PTU | IEN | M0))  /* sys_nirq2 */ \
++	MV(CP(SYS_BOOT0) , ( PTU | IEN | M3))  /* gpio_184 */ \
++	MV(CP(SYS_BOOT1) , ( M3))  /* gpio_185 */ \
++	MV(CP(SYS_BOOT2) , ( PTD | IEN | M3))  /* gpio_186 */ \
++	MV(CP(SYS_BOOT3) , ( M3))  /* gpio_187 */ \
++	MV(CP(SYS_BOOT4) , ( M3))  /* gpio_188 */ \
++	MV(CP(SYS_BOOT5) , ( PTD | IEN | M3))  /* gpio_189 */ \
++	MV(CP(DPM_EMU0) , ( IEN | M0))  /* dpm_emu0 */ \
++	MV(CP(DPM_EMU1) , ( IEN | M0))  /* dpm_emu1 */ \
++	MV(CP(DPM_EMU2) , ( IEN | M0))  /* dpm_emu2 */ \
++	MV(CP(DPM_EMU3) , ( IEN | M5))  /* dispc2_data10 */ \
++	MV(CP(DPM_EMU4) , ( IEN | M5))  /* dispc2_data9 */ \
++	MV(CP(DPM_EMU5) , ( IEN | M5))  /* dispc2_data16 */ \
++	MV(CP(DPM_EMU6) , ( IEN | M5))  /* dispc2_data17 */ \
++	MV(CP(DPM_EMU7) , ( IEN | M5))  /* dispc2_hsync */ \
++	MV(CP(DPM_EMU8) , ( IEN | M5))  /* dispc2_pclk */ \
++	MV(CP(DPM_EMU9) , ( IEN | M5))  /* dispc2_vsync */ \
++	MV(CP(DPM_EMU10) , ( IEN | M5))  /* dispc2_de */ \
++	MV(CP(DPM_EMU11) , ( IEN | M5))  /* dispc2_data8 */ \
++	MV(CP(DPM_EMU12) , ( IEN | M5))  /* dispc2_data7 */ \
++	MV(CP(DPM_EMU13) , ( IEN | M5))  /* dispc2_data6 */ \
++	MV(CP(DPM_EMU14) , ( IEN | M5))  /* dispc2_data5 */ \
++	MV(CP(DPM_EMU15) , ( IEN | M5))  /* dispc2_data4 */ \
++	MV(CP(DPM_EMU16) , ( M3))  /* gpio_27 */ \
++	MV(CP(DPM_EMU17) , ( IEN | M5))  /* dispc2_data2 */ \
++	MV(CP(DPM_EMU18) , ( IEN | M5))  /* dispc2_data1 */ \
++	MV(CP(DPM_EMU19) , ( IEN | M5))  /* dispc2_data0 */ \
++	MV1(WK(PAD0_SIM_IO) , ( IEN | M0))  /* sim_io */ \
++	MV1(WK(PAD1_SIM_CLK) , ( M0))  /* sim_clk */ \
++	MV1(WK(PAD0_SIM_RESET) , ( M0))  /* sim_reset */ \
++	MV1(WK(PAD1_SIM_CD) , ( PTU | IEN | M0))  /* sim_cd */ \
++	MV1(WK(PAD0_SIM_PWRCTRL) , ( M0))  /* sim_pwrctrl */ \
++	MV1(WK(PAD1_SR_SCL) , ( PTU | IEN | M0))  /* sr_scl */ \
++	MV1(WK(PAD0_SR_SDA) , ( PTU | IEN | M0))  /* sr_sda */ \
++	MV1(WK(PAD1_FREF_XTAL_IN) , ( M0))  /* # */ \
++	MV1(WK(PAD0_FREF_SLICER_IN) , ( M0))  /* fref_slicer_in */ \
++	MV1(WK(PAD1_FREF_CLK_IOREQ) , ( M0))  /* fref_clk_ioreq */ \
++	MV1(WK(PAD0_FREF_CLK0_OUT) , ( M2))  /* sys_drm_msecure */ \
++	MV1(WK(PAD1_FREF_CLK3_REQ) , ( PTU | IEN | M0))  /* # */ \
++	MV1(WK(PAD0_FREF_CLK3_OUT) , ( M0))  /* fref_clk3_out */ \
++	MV1(WK(PAD1_FREF_CLK4_REQ) , ( PTU | IEN | M0))  /* # */ \
++	MV1(WK(PAD0_FREF_CLK4_OUT) , ( M0))  /* # */ \
++	MV1(WK(PAD1_SYS_32K) , ( IEN | M0))  /* sys_32k */ \
++	MV1(WK(PAD0_SYS_NRESPWRON) , ( M0))  /* sys_nrespwron */ \
++	MV1(WK(PAD1_SYS_NRESWARM) , ( M0))  /* sys_nreswarm */ \
++	MV1(WK(PAD0_SYS_PWR_REQ) , ( PTU | M0))  /* sys_pwr_req */ \
++	MV1(WK(PAD1_SYS_PWRON_RESET) , ( M3))  /* gpio_wk29 */ \
++	MV1(WK(PAD0_SYS_BOOT6) , ( IEN | M3))  /* gpio_wk9 */ \
++	MV1(WK(PAD1_SYS_BOOT7) , ( IEN | M3))  /* gpio_wk10 */ \
++	MV1(WK(PAD1_FREF_CLK3_REQ),     (M3)) /* gpio_wk30 */ \
++	MV1(WK(PAD1_FREF_CLK4_REQ),     (M3)) /* gpio_wk7 */ \
++	MV1(WK(PAD0_FREF_CLK4_OUT),     (M3)) /* gpio_wk8 */
++
++#define MUX_DEFAULT_OMAP4_ALL() \
++  	MV(CP(GPMC_AD0),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat0 */ \
++	MV(CP(GPMC_AD1),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat1 */ \
++	MV(CP(GPMC_AD2),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat2 */ \
++	MV(CP(GPMC_AD3),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat3 */ \
++	MV(CP(GPMC_AD4),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat4 */ \
++	MV(CP(GPMC_AD5),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat5 */ \
++	MV(CP(GPMC_AD6),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat6 */ \
++	MV(CP(GPMC_AD7),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_dat7 */ \
++	MV(CP(GPMC_AD8),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_32 */ \
++	MV(CP(GPMC_AD9),	(M3_SAFE)) /* gpio_33 */ \
++	MV(CP(GPMC_AD10),	(M3_SAFE)) /* gpio_34 */ \
++	MV(CP(GPMC_AD11),	(M3_SAFE)) /* gpio_35 */ \
++	MV(CP(GPMC_AD12),	(M3_SAFE)) /* gpio_36 */ \
++	MV(CP(GPMC_AD13),	(PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_37 */ \
++	MV(CP(GPMC_AD14),	(PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_38 */ \
++	MV(CP(GPMC_AD15),	(PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
++	MV(CP(GPMC_A16),	(M3_SAFE)) /* gpio_40 */ \
++	MV(CP(GPMC_A17),	(M3_SAFE)) /* gpio_41 */ \
++	MV(CP(GPMC_A18),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row6 */ \
++	MV(CP(GPMC_A19),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row7 */ \
++	MV(CP(GPMC_A20),	(M3_SAFE)) /* gpio_44 */ \
++	MV(CP(GPMC_A21),	(M3_SAFE)) /* gpio_45 */ \
++	MV(CP(GPMC_A22),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col6 */ \
++	MV(CP(GPMC_A23),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col7 */ \
++	MV(CP(GPMC_A24),	(M3_SAFE)) /* gpio_48 */ \
++	MV(CP(GPMC_A25),	(M3_SAFE)) /* gpio_49 */ \
++	MV(CP(GPMC_NCS0),	(M0)) /* gpmc_ncs0 */ \
++	MV(CP(GPMC_NCS1),	(M3_SAFE)) /* gpio_51 */ \
++	MV(CP(GPMC_NCS2),	(M3_SAFE)) /* gpio_52 */ \
++	MV(CP(GPMC_NCS3),	(M3_SAFE)) /* gpio_53 */ \
++	MV(CP(GPMC_NWP),	(M0_SAFE)) /* gpmc_nwp */ \
++	MV(CP(GPMC_CLK),	(M3_SAFE)) /* gpio_55 */ \
++	MV(CP(GPMC_NADV_ALE),	(M0)) /* gpmc_nadv_ale */ \
++	MV(CP(GPMC_NOE),	(PTU | OFF_EN | OFF_OUT_PTD | M1)) /* sdmmc2_clk */ \
++	MV(CP(GPMC_NWE),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* sdmmc2_cmd */ \
++	MV(CP(GPMC_NBE0_CLE),	(M0)) /* gpmc_nbe0_cle*/ \
++	MV(CP(GPMC_NBE1),	(M3_SAFE)) /* gpio_60 */ \
++	MV(CP(GPMC_WAIT0),	(M0)) /* gpmc_wait */ \
++	MV(CP(GPMC_WAIT1),	(PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_39 */ \
++	MV(CP(C2C_DATA11),	(M3_SAFE)) /* gpio_100 */ \
++	MV(CP(C2C_DATA12),	(M1_SAFE)) /* dsi1_te0 */ \
++	MV(CP(C2C_DATA13),	(M3_SAFE)) /* gpio_102 */ \
++	MV(CP(C2C_DATA14),	(M1_SAFE)) /* dsi2_te0 */ \
++	MV(CP(C2C_DATA15),	(M3_SAFE)) /* gpio_104 */ \
++	MV(CP(HDMI_HPD),	(M0_SAFE)) /* hdmi_hpd */ \
++	MV(CP(HDMI_CEC),	(M0_SAFE)) /* hdmi_cec */ \
++	MV(CP(HDMI_DDC_SCL),	(M0_SAFE)) /* hdmi_ddc_scl */ \
++	MV(CP(HDMI_DDC_SDA),	(M0_SAFE)) /* hdmi_ddc_sda */ \
++	MV(CP(CSI21_DX0),	(M0_SAFE)) /* csi21_dx0 */ \
++	MV(CP(CSI21_DY0),	(M0_SAFE)) /* csi21_dy0 */ \
++	MV(CP(CSI21_DX1),	(M0_SAFE)) /* csi21_dx1 */ \
++	MV(CP(CSI21_DY1),	(M0_SAFE)) /* csi21_dy1 */ \
++	MV(CP(CSI21_DX2),	(M0_SAFE)) /* csi21_dx2 */ \
++	MV(CP(CSI21_DY2),	(M0_SAFE)) /* csi21_dy2 */ \
++	MV(CP(CSI21_DX3),	(M0_SAFE)) /* csi21_dx3 */ \
++	MV(CP(CSI21_DY3),	(M0_SAFE)) /* csi21_dy3 */ \
++	MV(CP(CSI21_DX4),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_75 */ \
++	MV(CP(CSI21_DY4),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpi_76 */ \
++	MV(CP(CSI22_DX0),	(M0_SAFE)) /* csi22_dx0 */ \
++	MV(CP(CSI22_DY0),	(M0_SAFE)) /* csi22_dy0 */ \
++	MV(CP(CSI22_DX1),	(M0_SAFE)) /* csi22_dx1 */ \
++	MV(CP(CSI22_DY1),	(M0_SAFE)) /* csi22_dy1 */ \
++	MV(CP(CAM_SHUTTER),	(PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_shutter */ \
++	MV(CP(CAM_STROBE),	(PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* cam_strobe */ \
++	MV(CP(CAM_GLOBALRESET),	(PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)) /* gpio_83 */ \
++	MV(CP(USBB1_ULPITLL_CLK),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_clk */ \
++	MV(CP(USBB1_ULPITLL_STP),	(PTU | OFF_EN | OFF_OUT_PTD | M4)) /* usbb1_ulpiphy_stp */ \
++	MV(CP(USBB1_ULPITLL_DIR),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dir */ \
++	MV(CP(USBB1_ULPITLL_NXT),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_nxt */ \
++	MV(CP(USBB1_ULPITLL_DAT0),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat0 */ \
++	MV(CP(USBB1_ULPITLL_DAT1),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat1 */ \
++	MV(CP(USBB1_ULPITLL_DAT2),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat2 */ \
++	MV(CP(USBB1_ULPITLL_DAT3),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat3 */ \
++	MV(CP(USBB1_ULPITLL_DAT4),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat4 */ \
++	MV(CP(USBB1_ULPITLL_DAT5),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat5 */ \
++	MV(CP(USBB1_ULPITLL_DAT6),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat6 */ \
++	MV(CP(USBB1_ULPITLL_DAT7),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)) /* usbb1_ulpiphy_dat7 */ \
++	MV(CP(USBB1_HSIC_DATA),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_data */ \
++	MV(CP(USBB1_HSIC_STROBE),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usbb1_hsic_strobe */ \
++	MV(CP(USBC1_ICUSB_DP),	(M0_SAFE)) /* usbc1_icusb_dp */ \
++	MV(CP(USBC1_ICUSB_DM),	(M0_SAFE)) /* usbc1_icusb_dm */ \
++	MV(CP(SDMMC1_CLK),	(PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc1_clk */ \
++	MV(CP(SDMMC1_CMD),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_cmd */ \
++	MV(CP(SDMMC1_DAT0),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat0 */ \
++	MV(CP(SDMMC1_DAT1),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat1 */ \
++	MV(CP(SDMMC1_DAT2),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat2 */ \
++	MV(CP(SDMMC1_DAT3),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat3 */ \
++	MV(CP(SDMMC1_DAT4),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat4 */ \
++	MV(CP(SDMMC1_DAT5),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat5 */ \
++	MV(CP(SDMMC1_DAT6),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat6 */ \
++	MV(CP(SDMMC1_DAT7),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc1_dat7 */ \
++	MV(CP(ABE_MCBSP2_CLKX),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_clkx */ \
++	MV(CP(ABE_MCBSP2_DR),	(IEN | OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dr */ \
++	MV(CP(ABE_MCBSP2_DX),	(OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp2_dx */ \
++	MV(CP(ABE_MCBSP2_FSX),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp2_fsx */ \
++	MV(CP(ABE_MCBSP1_CLKX),	(M1_SAFE)) /* abe_slimbus1_clock */ \
++	MV(CP(ABE_MCBSP1_DR),	(M1_SAFE)) /* abe_slimbus1_data */ \
++	MV(CP(ABE_MCBSP1_DX),	(OFF_EN | OFF_OUT_PTD | M0)) /* abe_mcbsp1_dx */ \
++	MV(CP(ABE_MCBSP1_FSX),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* abe_mcbsp1_fsx */ \
++	MV(CP(ABE_PDM_UL_DATA),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_ul_data */ \
++	MV(CP(ABE_PDM_DL_DATA),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_dl_data */ \
++	MV(CP(ABE_PDM_FRAME),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_frame */ \
++	MV(CP(ABE_PDM_LB_CLK),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_pdm_lb_clk */ \
++	MV(CP(ABE_CLKS),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* abe_clks */ \
++	MV(CP(ABE_DMIC_CLK1),	(M0_SAFE)) /* abe_dmic_clk1 */ \
++	MV(CP(ABE_DMIC_DIN1),	(M0_SAFE)) /* abe_dmic_din1 */ \
++	MV(CP(ABE_DMIC_DIN2),	(M0_SAFE)) /* abe_dmic_din2 */ \
++	MV(CP(ABE_DMIC_DIN3),	(M0_SAFE)) /* abe_dmic_din3 */ \
++	MV(CP(UART2_CTS),	(PTU | IEN | M0)) /* uart2_cts */ \
++	MV(CP(UART2_RTS),	(M0)) /* uart2_rts */ \
++	MV(CP(UART2_RX),	(PTU | IEN | M0)) /* uart2_rx */ \
++	MV(CP(UART2_TX),	(M0)) /* uart2_tx */ \
++	MV(CP(HDQ_SIO),	(M3_SAFE)) /* gpio_127 */ \
++	MV(CP(I2C1_SCL),	(PTU | IEN | M0)) /* i2c1_scl */ \
++	MV(CP(I2C1_SDA),	(PTU | IEN | M0)) /* i2c1_sda */ \
++	MV(CP(I2C2_SCL),	(PTU | IEN | M0)) /* i2c2_scl */ \
++	MV(CP(I2C2_SDA),	(PTU | IEN | M0)) /* i2c2_sda */ \
++	MV(CP(I2C3_SCL),	(PTU | IEN | M0)) /* i2c3_scl */ \
++	MV(CP(I2C3_SDA),	(PTU | IEN | M0)) /* i2c3_sda */ \
++	MV(CP(I2C4_SCL),	(PTU | IEN | M0)) /* i2c4_scl */ \
++	MV(CP(I2C4_SDA),	(PTU | IEN | M0)) /* i2c4_sda */ \
++	MV(CP(MCSPI1_CLK),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_clk */ \
++	MV(CP(MCSPI1_SOMI),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_somi */ \
++	MV(CP(MCSPI1_SIMO),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_simo */ \
++	MV(CP(MCSPI1_CS0),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi1_cs0 */ \
++	MV(CP(MCSPI1_CS1),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0_SAFE)) /* mcspi1_cs1 */ \
++	MV(CP(MCSPI1_CS2),	(OFF_EN | OFF_OUT_PTU | M3)) /* gpio_139 */ \
++	MV(CP(MCSPI1_CS3),	(M3_SAFE)) /* gpio_140 */ \
++	MV(CP(UART3_CTS_RCTX),	(PTU | IEN | M0)) /* uart3_tx */ \
++	MV(CP(UART3_RTS_SD),	(M0)) /* uart3_rts_sd */ \
++	MV(CP(UART3_RX_IRRX),	(IEN | M0)) /* uart3_rx */ \
++	MV(CP(UART3_TX_IRTX),	(M0)) /* uart3_tx */ \
++	MV(CP(SDMMC5_CLK),	(PTU | OFF_EN | OFF_OUT_PTD | M0)) /* sdmmc5_clk */ \
++	MV(CP(SDMMC5_CMD),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_cmd */ \
++	MV(CP(SDMMC5_DAT0),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat0 */ \
++	MV(CP(SDMMC5_DAT1),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat1 */ \
++	MV(CP(SDMMC5_DAT2),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat2 */ \
++	MV(CP(SDMMC5_DAT3),	(PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* sdmmc5_dat3 */ \
++	MV(CP(MCSPI4_CLK),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_clk */ \
++	MV(CP(MCSPI4_SIMO),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_simo */ \
++	MV(CP(MCSPI4_SOMI),	(IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_somi */ \
++	MV(CP(MCSPI4_CS0),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* mcspi4_cs0 */ \
++	MV(CP(UART4_RX),	(IEN | M0)) /* uart4_rx */ \
++	MV(CP(UART4_TX),	(M0)) /* uart4_tx */ \
++	MV(CP(USBB2_ULPITLL_CLK),	(M3)) /* gpio_157 */ \
++	MV(CP(USBB2_ULPITLL_STP),	(M5)) /* dispc2_data23 */ \
++	MV(CP(USBB2_ULPITLL_DIR),	(M5)) /* dispc2_data22 */ \
++	MV(CP(USBB2_ULPITLL_NXT),	(M5)) /* dispc2_data21 */ \
++	MV(CP(USBB2_ULPITLL_DAT0),	(M5)) /* dispc2_data20 */ \
++	MV(CP(USBB2_ULPITLL_DAT1),	(M5)) /* dispc2_data19 */ \
++	MV(CP(USBB2_ULPITLL_DAT2),	(M5)) /* dispc2_data18 */ \
++	MV(CP(USBB2_ULPITLL_DAT3),	(M5)) /* dispc2_data15 */ \
++	MV(CP(USBB2_ULPITLL_DAT4),	(M5)) /* dispc2_data14 */ \
++	MV(CP(USBB2_ULPITLL_DAT5),	(M5)) /* dispc2_data13 */ \
++	MV(CP(USBB2_ULPITLL_DAT6),	(M5)) /* dispc2_data12 */ \
++	MV(CP(USBB2_ULPITLL_DAT7),	(M5)) /* dispc2_data11 */ \
++	MV(CP(USBB2_HSIC_DATA),	(OFF_EN | OFF_OUT_PTU | M3)) /* gpio_169 */ \
++	MV(CP(USBB2_HSIC_STROBE),	(OFF_EN | OFF_OUT_PTU | M3)) /* gpio_170 */ \
++	MV(CP(UNIPRO_TX0),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col0 */ \
++	MV(CP(UNIPRO_TY0),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col1 */ \
++	MV(CP(UNIPRO_TX1),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col2 */ \
++	MV(CP(UNIPRO_TY1),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_col3 */ \
++	MV(CP(UNIPRO_TX2),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_0 */ \
++	MV(CP(UNIPRO_TY2),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)) /* gpio_1 */ \
++	MV(CP(UNIPRO_RX0),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row0 */ \
++	MV(CP(UNIPRO_RY0),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row1 */ \
++	MV(CP(UNIPRO_RX1),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row2 */ \
++	MV(CP(UNIPRO_RY1),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row3 */ \
++	MV(CP(UNIPRO_RX2),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row4 */ \
++	MV(CP(UNIPRO_RY2),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M1)) /* kpd_row5 */ \
++	MV(CP(USBA0_OTG_CE),	(PTU | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)) /* usba0_otg_ce */ \
++	MV(CP(USBA0_OTG_DP),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dp */ \
++	MV(CP(USBA0_OTG_DM),	(PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)) /* usba0_otg_dm */ \
++	MV(CP(FREF_CLK1_OUT),	(M0_SAFE)) /* fref_clk1_out */ \
++	MV(CP(FREF_CLK2_OUT),	(M0_SAFE)) /* fref_clk2_out */ \
++	MV(CP(SYS_NIRQ1),	(PTU | IEN | M0)) /* sys_nirq1 */ \
++	MV(CP(SYS_NIRQ2),	(PTU | IEN | M0)) /* sys_nirq2 */ \
++	MV(CP(SYS_BOOT0),	(M3_SAFE)) /* gpio_184 */ \
++	MV(CP(SYS_BOOT1),	(M3_SAFE)) /* gpio_185 */ \
++	MV(CP(SYS_BOOT2),	(M3_SAFE)) /* gpio_186 */ \
++	MV(CP(SYS_BOOT3),	(M3_SAFE)) /* gpio_187 */ \
++	MV(CP(SYS_BOOT4),	(M3_SAFE)) /* gpio_188 */ \
++	MV(CP(SYS_BOOT5),	(M3_SAFE)) /* gpio_189 */ \
++	MV(CP(DPM_EMU0),	(M0_SAFE)) /* dpm_emu0 */ \
++	MV(CP(DPM_EMU1),	(M0_SAFE)) /* dpm_emu1 */ \
++	MV(CP(DPM_EMU2),	(M0_SAFE)) /* dpm_emu2 */ \
++	MV(CP(DPM_EMU3),	(M5)) /* dispc2_data10 */ \
++	MV(CP(DPM_EMU4),	(M5)) /* dispc2_data9 */ \
++	MV(CP(DPM_EMU5),	(M5)) /* dispc2_data16 */ \
++	MV(CP(DPM_EMU6),	(M5)) /* dispc2_data17 */ \
++	MV(CP(DPM_EMU7),	(M5)) /* dispc2_hsync */ \
++	MV(CP(DPM_EMU8),	(M5)) /* dispc2_pclk */ \
++	MV(CP(DPM_EMU9),	(M5)) /* dispc2_vsync */ \
++	MV(CP(DPM_EMU10),	(M5)) /* dispc2_de */ \
++	MV(CP(DPM_EMU11),	(M5)) /* dispc2_data8 */ \
++	MV(CP(DPM_EMU12),	(M5)) /* dispc2_data7 */ \
++	MV(CP(DPM_EMU13),	(M5)) /* dispc2_data6 */ \
++	MV(CP(DPM_EMU14),	(M5)) /* dispc2_data5 */ \
++	MV(CP(DPM_EMU15),	(M5)) /* dispc2_data4 */ \
++	MV(CP(DPM_EMU16),	(M5)) /* dispc2_data3/dmtimer8_pwm_evt */ \
++	MV(CP(DPM_EMU17),	(M5)) /* dispc2_data2 */ \
++	MV(CP(DPM_EMU18),	(M5)) /* dispc2_data1 */ \
++	MV(CP(DPM_EMU19),	(M5)) /* dispc2_data0 */ \
++	MV1(WK(PAD0_SIM_IO),	(M0_SAFE)) /* sim_io */ \
++	MV1(WK(PAD1_SIM_CLK),	(M0_SAFE)) /* sim_clk */ \
++	MV1(WK(PAD0_SIM_RESET),	(M0_SAFE)) /* sim_reset */ \
++	MV1(WK(PAD1_SIM_CD),	(M0_SAFE)) /* sim_cd */ \
++	MV1(WK(PAD0_SIM_PWRCTRL),	(M0_SAFE)) /* sim_pwrctrl */ \
++	MV1(WK(PAD1_SR_SCL),	(PTU | IEN | M0)) /* sr_scl */ \
++	MV1(WK(PAD0_SR_SDA),	(PTU | IEN | M0)) /* sr_sda */ \
++	MV1(WK(PAD1_FREF_XTAL_IN),	(M0_SAFE)) /* # */ \
++	MV1(WK(PAD0_FREF_SLICER_IN),	(M0_SAFE)) /* fref_slicer_in */ \
++	MV1(WK(PAD1_FREF_CLK_IOREQ),	(M0_SAFE)) /* fref_clk_ioreq */ \
++	MV1(WK(PAD0_FREF_CLK0_OUT),	(M0)) /* sys_drm_msecure */ \
++	MV1(WK(PAD1_FREF_CLK3_REQ),	(M0)) /* # */ \
++	MV1(WK(PAD0_FREF_CLK3_OUT),	(M0_SAFE)) /* fref_clk3_out */ \
++	MV1(WK(PAD1_FREF_CLK4_REQ),	(M0_SAFE)) /* # */ \
++	MV1(WK(PAD0_FREF_CLK4_OUT),	(M0_SAFE)) /* # */ \
++	MV1(WK(PAD1_SYS_32K),	(IEN | M0_SAFE)) /* sys_32k */ \
++	MV1(WK(PAD0_SYS_NRESPWRON),	(IEN | M0_SAFE)) /* sys_nrespwron */ \
++	MV1(WK(PAD1_SYS_NRESWARM),	(IEN | M0_SAFE)) /* sys_nreswarm */ \
++	MV1(WK(PAD0_SYS_PWR_REQ),	(M0_SAFE)) /* sys_pwr_req */ \
++	MV1(WK(PAD1_SYS_PWRON_RESET),	(M3_SAFE)) /* gpio_wk29 */ \
++	MV1(WK(PAD0_SYS_BOOT6),	(M3_SAFE)) /* gpio_wk9 */ \
++	MV1(WK(PAD1_SYS_BOOT7),	(M3_SAFE)) /* gpio_wk10 */ \
++	MV1(WK(PAD1_JTAG_TCK),	(IEN | M0)) /* jtag_tck */ \
++	MV1(WK(PAD0_JTAG_RTCK),	(M0)) /* jtag_rtck */ \
++	MV1(WK(PAD1_JTAG_TMS_TMSC),	(IEN | M0)) /* jtag_tms_tmsc */ \
++	MV1(WK(PAD0_JTAG_TDI),	(IEN | M0)) /* jtag_tdi */ \
++	MV1(WK(PAD1_JTAG_TDO),	(M0)) 		  /* jtag_tdo */ 
++
++/**********************************************************
++ * Routine: set_muxconf_regs
++ * Description: Setting up the configuration Mux registers
++ *              specific to the hardware. Many pins need
++ *              to be moved from protect to primary mode.
++ *********************************************************/
++void set_muxconf_regs(void)
++{
++	MUX_DEFAULT_OMAP4();
++	return;
++}
++
++/******************************************************************************
++ * Routine: update_mux()
++ * Description:Update balls which are different between boards.  All should be
++ *             updated to match functionality.  However, I'm only updating ones
++ *             which I'll be using for now.  When power comes into play they
++ *             all need updating.
++ *****************************************************************************/
++void update_mux(u32 btype, u32 mtype)
++{
++	/* REVISIT  */
++	return;
++
++}
++
++/* optionally do something like blinking LED */
++void board_hang (void)
++{ while (0) {};}
++
++int nand_init(void)
++{
++	return 0;
++}
++void reset_phy(unsigned int base)
++{
++	*(volatile int*)(base + IODFT_TLGC) |= (1 << 10);
++}
+diff -uNr x-load-f243938.orig/board/omap4430panda/platform.S x-load-f243938/board/omap4430panda/platform.S
+--- x-load-f243938.orig/board/omap4430panda/platform.S	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/board/omap4430panda/platform.S	2012-06-07 14:45:39.445648666 -0300
+@@ -0,0 +1,51 @@
++/*
++ * Board specific setup info
++ *
++ * (C) Copyright 2004-2006
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/mem.h>
++#include <asm/arch/clocks.h>
++
++_TEXT_BASE:
++	.word	TEXT_BASE	/* sdram load addr from config.mk */
++
++.globl lowlevel_init
++lowlevel_init:
++	ldr	sp,	SRAM_STACK
++        str     ip,	[sp]    /* stash old link register */
++	mov	ip,	lr	/* save link reg across call */
++	bl      s_init          /* go setup pll,mux,memory */
++        ldr     ip,	[sp]    /* restore save ip */
++	mov	lr,	ip	/* restore link reg */
++
++	/* back to arch calling code */
++	mov	pc,	lr
++
++	/* the literal pools origin */
++	.ltorg
++
++SRAM_STACK:
++	.word LOW_LEVEL_SRAM_STACK
+diff -uNr x-load-f243938.orig/board/omap4430panda/syslib.c x-load-f243938/board/omap4430panda/syslib.c
+--- x-load-f243938.orig/board/omap4430panda/syslib.c	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/board/omap4430panda/syslib.c	2012-06-07 14:45:39.445648666 -0300
+@@ -0,0 +1,73 @@
++/*
++ * (C) Copyright 2006
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/cpu.h>
++#include <asm/io.h>
++#include <asm/arch/bits.h>
++#include <asm/arch/mem.h>
++#include <asm/arch/clocks.h>
++#include <asm/arch/sys_proto.h>
++#include <asm/arch/sys_info.h>
++
++/************************************************************
++ * sdelay() - simple spin loop.  Will be constant time as
++ *  its generally used in bypass conditions only.  This
++ *  is necessary until timers are accessible.
++ *
++ *  not inline to increase chances its in cache when called
++ *************************************************************/
++void sdelay(unsigned long loops)
++{
++	__asm__ volatile ("1:\n" "subs %0, %1, #1\n"  
++					  "bne 1b":"=r" (loops):"0"(loops));
++}
++
++/*****************************************************************
++ * sr32 - clear & set a value in a bit range for a 32 bit address
++ *****************************************************************/
++void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
++{
++	u32 tmp, msk = 0;
++	msk = 1 << num_bits;
++	--msk;
++	tmp = __raw_readl(addr) & ~(msk << start_bit);
++	tmp |=  value << start_bit;
++	__raw_writel(tmp, addr);
++}
++
++/*********************************************************************
++ * wait_on_value() - common routine to allow waiting for changes in
++ *   volatile regs.
++ *********************************************************************/
++u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
++{
++	u32 i = 0, val;
++	do {
++		++i;
++		val = __raw_readl(read_addr) & read_bit_mask;
++		if (val == match_value)
++			return (1);
++		if (i == bound)
++			return (0);
++	} while (1);
++}
++
+diff -uNr x-load-f243938.orig/board/omap4430panda/x-load.lds x-load-f243938/board/omap4430panda/x-load.lds
+--- x-load-f243938.orig/board/omap4430panda/x-load.lds	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/board/omap4430panda/x-load.lds	2012-06-07 14:45:39.445648666 -0300
+@@ -0,0 +1,54 @@
++/*
++ * November 2006 - Changed to support 3430sdp device 
++ * Copyright (c) 2004-2006 Texas Instruments 
++ *
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++	. = 0x00000000;
++
++	. = ALIGN(4);
++	.text      :
++	{
++	  cpu/omap4/start.o	(.text)
++	  *(.text)
++	}
++
++	. = ALIGN(4);
++	.rodata : { *(.rodata) }
++
++	. = ALIGN(4);
++	.data : { *(.data) }
++
++	. = ALIGN(4);
++	.got : { *(.got) }
++
++	. = ALIGN(4);
++	__bss_start = .;
++	.bss : { *(.bss) }
++	_end = .;
++}
+diff -uNr x-load-f243938.orig/board/overo/config.mk x-load-f243938/board/overo/config.mk
+--- x-load-f243938.orig/board/overo/config.mk	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/board/overo/config.mk	2012-06-07 14:45:39.445648666 -0300
+@@ -10,11 +10,11 @@
+ # 8000'0000 (bank0)
+ 
+ # For use if you want X-Loader to relocate from SRAM to DDR
+-TEXT_BASE = 0x80e80000
++#TEXT_BASE = 0x80e80000
+ 
+ # For XIP in 64K of SRAM or debug (GP device has it all availabe)
+ # SRAM 40200000-4020FFFF base
+ # initial stack at 0x4020fffc used in s_init (below xloader).
+ # The run time stack is (above xloader, 2k below)
+ # If any globals exist there needs to be room for them also
+-#TEXT_BASE = 0x40200800
++TEXT_BASE = 0x40200800
+diff -uNr x-load-f243938.orig/board/overo/overo.c x-load-f243938/board/overo/overo.c
+--- x-load-f243938.orig/board/overo/overo.c	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/board/overo/overo.c	2012-06-07 14:45:39.445648666 -0300
+@@ -30,14 +30,21 @@
+ #include <command.h>
+ #include <part.h>
+ #include <fat.h>
++#include <i2c.h>
+ #include <asm/arch/cpu.h>
+ #include <asm/arch/bits.h>
++#include <asm/arch/gpio.h>
+ #include <asm/arch/mux.h>
+ #include <asm/arch/sys_proto.h>
+ #include <asm/arch/sys_info.h>
+ #include <asm/arch/clocks.h>
+ #include <asm/arch/mem.h>
+ 
++/* params for 37XX */
++#define CORE_DPLL_PARAM_M2	0x09
++#define CORE_DPLL_PARAM_M	0x360
++#define CORE_DPLL_PARAM_N	0xC
++
+ /* Used to index into DPLL parameter tables */
+ struct dpll_param {
+ 	unsigned int m;
+@@ -59,6 +66,16 @@
+ #define __raw_readw(a)		(*(volatile unsigned short *)(a))
+ #define __raw_writew(v, a)	(*(volatile unsigned short *)(a) = (v))
+ 
++static char *rev_s[CPU_3XX_MAX_REV] = {
++				"1.0",
++				"2.0",
++				"2.1",
++				"3.0",
++				"3.1",
++				"UNKNOWN",
++				"UNKNOWN",
++				"3.1.2"};
++
+ /*******************************************************
+  * Routine: delay
+  * Description: spinning delay to use before udelay works
+@@ -109,6 +126,7 @@
+ u32 get_mem_type(void)
+ {
+ 	u32   mem_type = get_sysboot_value();
++
+ 	switch (mem_type) {
+ 	case 0:
+ 	case 2:
+@@ -151,21 +169,158 @@
+ }
+ 
+ /******************************************
+- * get_cpu_rev(void) - extract version info
++ * get_cpu_type(void) - extract cpu info
+  ******************************************/
+-u32 get_cpu_rev(void)
++u32 get_cpu_type(void)
++{
++	return __raw_readl(CONTROL_OMAP_STATUS);
++}
++
++/******************************************
++ * get_cpu_id(void) - extract cpu id
++ * returns 0 for ES1.0, cpuid otherwise
++ ******************************************/
++u32 get_cpu_id(void)
+ {
+ 	u32 cpuid = 0;
+-	/* On ES1.0 the IDCODE register is not exposed on L4
+-	 * so using CPU ID to differentiate
+-	 * between ES2.0 and ES1.0.
++
++	/*
++	 * On ES1.0 the IDCODE register is not exposed on L4
++	 * so using CPU ID to differentiate between ES1.0 and > ES1.0.
+ 	 */
+-	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
+-	if ((cpuid  & 0xf) == 0x0)
+-		return CPU_3430_ES1;
++	__asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
++	if ((cpuid & 0xf) == 0x0) {
++		return 0;
++	} else {
++		/* Decode the IDs on > ES1.0 */
++		cpuid = __raw_readl(CONTROL_IDCODE);
++	}
++
++	return cpuid;
++}
++
++/******************************************
++ * get_cpu_family(void) - extract cpu info
++ ******************************************/
++u32 get_cpu_family(void)
++{
++	u16 hawkeye;
++	u32 cpu_family;
++	u32 cpuid = get_cpu_id();
++
++	if (cpuid == 0)
++		return CPU_OMAP34XX;
++
++	hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
++	switch (hawkeye) {
++	case HAWKEYE_OMAP34XX:
++		cpu_family = CPU_OMAP34XX;
++		break;
++	case HAWKEYE_AM35XX:
++		cpu_family = CPU_AM35XX;
++		break;
++	case HAWKEYE_OMAP36XX:
++		cpu_family = CPU_OMAP36XX;
++		break;
++	default:
++		cpu_family = CPU_OMAP34XX;
++	}
++
++	return cpu_family;
++}
++
++/******************************************
++ * get_cpu_rev(void) - extract version info
++ ******************************************/
++u32 get_cpu_rev(void)
++{
++	u32 cpuid = get_cpu_id();
++
++	if (cpuid == 0)
++		return CPU_3XX_ES10;
+ 	else
+-		return CPU_3430_ES2;
++		return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
++}
++
++/******************************************
++ * Print CPU information
++ ******************************************/
++int print_cpuinfo (void)
++{
++	char *cpu_family_s, *cpu_s, *sec_s;
++
++	switch (get_cpu_family()) {
++	case CPU_OMAP34XX:
++		cpu_family_s = "OMAP";
++		switch (get_cpu_type()) {
++		case OMAP3503:
++			cpu_s = "3503";
++			break;
++		case OMAP3515:
++			cpu_s = "3515";
++			break;
++		case OMAP3525:
++			cpu_s = "3525";
++			break;
++		case OMAP3530:
++			cpu_s = "3530";
++			break;
++		default:
++			cpu_s = "35XX";
++			break;
++		}
++		break;
++	case CPU_AM35XX:
++		cpu_family_s = "AM";
++		switch (get_cpu_type()) {
++		case AM3505:
++			cpu_s = "3505";
++			break;
++		case AM3517:
++			cpu_s = "3517";
++			break;
++		default:
++			cpu_s = "35XX";
++			break;
++		}
++		break;
++	case CPU_OMAP36XX:
++		cpu_family_s = "OMAP";
++		switch (get_cpu_type()) {
++		case OMAP3730:
++			cpu_s = "3630/3730";
++			break;
++		default:
++			cpu_s = "36XX/37XX";
++			break;
++		}
++		break;
++	default:
++		cpu_family_s = "OMAP";
++		cpu_s = "35XX";
++	}
+ 
++	switch (get_device_type()) {
++	case TST_DEVICE:
++		sec_s = "TST";
++		break;
++	case EMU_DEVICE:
++		sec_s = "EMU";
++		break;
++	case HS_DEVICE:
++		sec_s = "HS";
++		break;
++	case GP_DEVICE:
++		sec_s = "GP";
++		break;
++	default:
++		sec_s = "?";
++	}
++
++	printf("%s%s-%s ES%s\n",
++			cpu_family_s, cpu_s, sec_s, rev_s[get_cpu_rev()]);
++
++	return 0;
+ }
+ 
+ /******************************************
+@@ -190,6 +345,47 @@
+ }
+ 
+ /*****************************************************************
++ * Routine: get_board_revision
++ * Description: Returns the board revision
++ *****************************************************************/
++int get_board_revision(void)
++{
++	int revision;
++	unsigned char data;
++
++	/* board revisions <= R2410 connect 4030 irq_1 to gpio112             */
++	/* these boards should return a revision number of 0                  */
++	/* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
++	data = 0x01;
++	i2c_write(0x4B, 0x29, 1, &data, 1);
++	data = 0x0c;
++	i2c_write(0x4B, 0x2b, 1, &data, 1);
++	i2c_read(0x4B, 0x2a, 1, &data, 1);
++
++	if (!omap_request_gpio(112) &&
++	    !omap_request_gpio(113) &&
++	    !omap_request_gpio(115)) {
++
++		omap_set_gpio_direction(112, 1);
++		omap_set_gpio_direction(113, 1);
++		omap_set_gpio_direction(115, 1);
++
++		revision = omap_get_gpio_datain(115) << 2 |
++			   omap_get_gpio_datain(113) << 1 |
++			   omap_get_gpio_datain(112);
++
++		omap_free_gpio(112);
++		omap_free_gpio(113);
++		omap_free_gpio(115);
++	} else {
++		printf("Error: unable to acquire board revision GPIOs\n");
++		revision = -1;
++	}
++
++	return revision;
++}
++
++/*****************************************************************
+  * sr32 - clear & set a value in a bit range for a 32 bit address
+  *****************************************************************/
+ void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
+@@ -225,55 +421,84 @@
+  *********************************************************************/
+ void config_3430sdram_ddr(void)
+ {
+-        /* reset sdrc controller */
+-        __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
+-        wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
+-        __raw_writel(0, SDRC_SYSCONFIG);
+-
+-        /* setup sdrc to ball mux */
+-        __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
+-
+-        /* SDRC put in weak */
+-//        (*(unsigned int*)0x6D00008C) = 0x00000020;
+-
+-        /* SDRC_MCFG0 register */
+-        (*(unsigned int*)0x6D000080) = 0x02584099;//from Micron
+-
+-        /* SDRC_ACTIM_CTRLA0 register */
+-//our value        (*(unsigned int*)0x6D00009c) = 0xa29db4c6;// for 166M
+-        (*(unsigned int*)0x6D00009c) = 0xaa9db4c6;// for 166M from rkw
+-
+-        /* SDRC_ACTIM_CTRLB0 register */
+-//from micron   (*(unsigned int*)0x6D0000a0) = 0x12214;// for 166M
+-
+-//        (*(unsigned int*)0x6D0000a0) = 0x00011417; our value
+-        (*(unsigned int*)0x6D0000a0) = 0x00011517;
+-
+-        /* SDRC_RFR_CTRL0 register */
+-//from micron   (*(unsigned int*)0x6D0000a4) =0x54601; // for 166M
+-
+-        (*(unsigned int*)0x6D0000a4) =0x0004DC01;
+-
+-        /* Disble Power Down of CKE cuz of 1 CKE on combo part */
+-        (*(unsigned int*)0x6D000070) = 0x00000081;
+-
+-        /* SDRC_Manual command register */
+-        (*(unsigned int*)0x6D0000a8) = 0x00000000; // NOP command
+-        delay(5000);
+-        (*(unsigned int*)0x6D0000a8) = 0x00000001; // Precharge command
+-        (*(unsigned int*)0x6D0000a8) = 0x00000002; // Auto-refresh command
+-        (*(unsigned int*)0x6D0000a8) = 0x00000002; // Auto-refresh command
+-
+-        /* SDRC MR0 register */
+-        (*(int*)0x6D000084) = 0x00000032; // Burst length =4
+-        // CAS latency = 3
+-        // Write Burst = Read Burst
+-        // Serial Mode
+-
+-        /* SDRC DLLA control register */
+-        (*(unsigned int*)0x6D000060) = 0x0000A;
+-        delay(0x20000); // some delay
++	/* reset sdrc controller */
++	__raw_writel(SOFTRESET, SDRC_SYSCONFIG);
++	wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
++	__raw_writel(0, SDRC_SYSCONFIG);
++
++	/* setup sdrc to ball mux */
++	__raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
++
++	switch (get_board_revision()) {
++	case 0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
++		__raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
++		__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
++		__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
++		__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
++		__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
++		__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
++		__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
++		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
++		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
++		break;
++	case 1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
++		__raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
++		__raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_0);
++		__raw_writel(SDP_SDRC_MDCFG_0_DDR_MICRON_XM, SDRC_MCFG_1);
++		__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
++		__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
++		__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
++		__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
++		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
++		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
++		break;
++	case 2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
++		__raw_writel(0x2, SDRC_CS_CFG); /* 256MB/bank */
++		__raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_0);
++		__raw_writel(SDP_SDRC_MDCFG_0_DDR_HYNIX, SDRC_MCFG_1);
++		__raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
++		__raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
++		__raw_writel(HYNIX_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
++		__raw_writel(HYNIX_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
++		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
++		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
++		break;
++	default:
++		__raw_writel(0x1, SDRC_CS_CFG); /* 128MB/bank */
++		__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
++		__raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_1);
++		__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_0);
++		__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_0);
++		__raw_writel(MICRON_V_ACTIMA_165, SDRC_ACTIM_CTRLA_1);
++		__raw_writel(MICRON_V_ACTIMB_165, SDRC_ACTIM_CTRLB_1);
++		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_0);
++		__raw_writel(SDP_3430_SDRC_RFR_CTRL_165MHz, SDRC_RFR_CTRL_1);
++	}
++
++	__raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
++
++	/* init sequence for mDDR/mSDR using manual commands (DDR is different) */
++	__raw_writel(CMD_NOP, SDRC_MANUAL_0);
++	__raw_writel(CMD_NOP, SDRC_MANUAL_1);
++
++	delay(5000);
++
++	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
++	__raw_writel(CMD_PRECHARGE, SDRC_MANUAL_1);
+ 
++	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
++	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
++
++	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
++	__raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_1);
++
++	/* set mr0 */
++	__raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
++	__raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_1);
++
++	/* set up dll */
++	__raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
++	delay(0x2000);	/* give time to lock */
+ }
+ #endif /* CFG_3430SDRAM_DDR */
+ 
+@@ -283,12 +508,14 @@
+  *************************************************************/
+ u32 get_osc_clk_speed(void)
+ {
+-	u32 start, cstart, cend, cdiff, val;
++	u32 start, cstart, cend, cdiff, cdiv, val;
+ 
+ 	val = __raw_readl(PRM_CLKSRC_CTRL);
+-	/* If SYS_CLK is being divided by 2, remove for now */
+-	val = (val & (~BIT7)) | BIT6;
+-	__raw_writel(val, PRM_CLKSRC_CTRL);
++
++	if (val & SYSCLKDIV_2)
++		cdiv = 2;
++	else
++		cdiv = 1;
+ 
+ 	/* enable timer2 */
+ 	val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
+@@ -312,6 +539,7 @@
+ 	while (__raw_readl(S32K_CR) < (start + 20));	/* wait for 40 cycles */
+ 	cend = __raw_readl(OMAP34XX_GPT1 + TCRR);	/* get end sys_clk count */
+ 	cdiff = cend - cstart;				/* get elapsed ticks */
++	cdiff *= cdiv;
+ 
+ 	/* based on number of ticks assign speed */
+ 	if (cdiff > 19000)
+@@ -363,17 +591,19 @@
+ 	osc_clk = get_osc_clk_speed();
+ 	get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
+ 
+-	sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
++	sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel);	/* set input crystal speed */
+ 
+ 	/* If the input clock is greater than 19.2M always divide/2 */
+ 	if (sys_clkin_sel > 2) {
+-		sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
+-		clk_index = sys_clkin_sel/2;
++		sr32(PRM_CLKSRC_CTRL, 6, 2, 2);	/* input clock divider */
++		clk_index = sys_clkin_sel / 2;
+ 	} else {
+-		sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
++		sr32(PRM_CLKSRC_CTRL, 6, 2, 1);	/* input clock divider */
+ 		clk_index = sys_clkin_sel;
+ 	}
+ 
++	sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
++
+ 	/* The DPLL tables are defined according to sysclk value and
+ 	 * silicon revision. The clk_index value will be used to get
+ 	 * the values for that input sysclk from the DPLL param table
+@@ -386,31 +616,35 @@
+ 	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
+ 	wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
+ 
+-	/* Getting the base address of Core DPLL param table*/
+-	dpll_param_p = (dpll_param *)get_core_dpll_param();
++	/* Getting the base address of Core DPLL param table */
++	dpll_param_p = (dpll_param *) get_core_dpll_param();
+ 	/* Moving it to the right sysclk and ES rev base */
+-	dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
++	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+ 	/* CORE DPLL */
+ 	/* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
+ 	sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
+ 	wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
++
++	 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
++	work. write another value and then default value. */
++	sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1);     /* m3x2 */
+ 	sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2);	/* m3x2 */
+ 	sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2);	/* Set M2 */
+ 	sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m);	/* Set M */
+ 	sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n);	/* Set N */
+-	sr32(CM_CLKSEL1_PLL, 6, 1, 0);			/* 96M Src */
++	sr32(CM_CLKSEL1_PLL, 6, 1, 0);	/* 96M Src */
+ 	sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV);	/* ssi */
+ 	sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV);	/* fsusb */
+ 	sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV);	/* l4 */
+ 	sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV);	/* l3 */
+-	sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV);		/* gfx */
+-	sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);		/* reset mgr */
++	sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV);	/* gfx */
++	sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM);	/* reset mgr */
+ 	sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
+-	sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);		/* lock mode */
++	sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK);	/* lock mode */
+ 	wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
+ 
+-	/* Getting the base address to PER  DPLL param table*/
+-	dpll_param_p = (dpll_param *)get_per_dpll_param();
++	/* Getting the base address to PER  DPLL param table */
++	dpll_param_p = (dpll_param *) get_per_dpll_param();
+ 	/* Moving it to the right sysclk base */
+ 	dpll_param_p = dpll_param_p + clk_index;
+ 	/* PER DPLL */
+@@ -420,29 +654,39 @@
+ 	sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2);	/* set M5 */
+ 	sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2);	/* set M4 */
+ 	sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2);	/* set M3 */
+-	sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2);	/* set M2 */
+-	sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m);	/* set m */
+-	sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n);	/* set n */
+-	sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
++
++	if (get_cpu_family() == CPU_OMAP36XX) {
++	        sr32(CM_CLKSEL3_PLL, 0, 5, CORE_DPLL_PARAM_M2); /* set M2 */
++	        sr32(CM_CLKSEL2_PLL, 8, 11, CORE_DPLL_PARAM_M); /* set m */
++	        sr32(CM_CLKSEL2_PLL, 0, 7, CORE_DPLL_PARAM_N);  /* set n */
++	} else {
++		sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2);	/* set M2 */
++		sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m);	/* set m */
++		sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n);	/* set n */
++	}
++
++	sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);	/* FREQSEL */
+ 	sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK);	/* lock mode */
+ 	wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
+ 
+-	/* Getting the base address to MPU DPLL param table*/
+-	dpll_param_p = (dpll_param *)get_mpu_dpll_param();
++	/* Getting the base address to MPU DPLL param table */
++	dpll_param_p = (dpll_param *) get_mpu_dpll_param();
++
+ 	/* Moving it to the right sysclk and ES rev base */
+-	dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
++	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
++
+ 	/* MPU DPLL (unlocked already) */
+ 	sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2);	/* Set M2 */
+ 	sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m);	/* Set M */
+ 	sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n);	/* Set N */
+ 	sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel);	/* FREQSEL */
+-	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
++	sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK);	/* lock mode */
+ 	wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
+ 
+-	/* Getting the base address to IVA DPLL param table*/
+-	dpll_param_p = (dpll_param *)get_iva_dpll_param();
++	/* Getting the base address to IVA DPLL param table */
++	dpll_param_p = (dpll_param *) get_iva_dpll_param();
+ 	/* Moving it to the right sysclk and ES rev base */
+-	dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
++	dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
+ 	/* IVA DPLL (set to 12*20=240MHz) */
+ 	sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
+ 	wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
+@@ -536,20 +780,11 @@
+ 
+ /*******************************************************
+  * Routine: misc_init_r
+- * Description: Init ethernet (done here so udelay works)
+  ********************************************************/
+ int misc_init_r(void)
+ {
+-#ifdef CONFIG_MMC
+-	/* REMOVE!! for proto boards only */
+-	/* set vaux2 to 2.8V */
+-	unsigned char byte = 0x20;
+-	i2c_write(0x4B, 0x76, 1, &byte, 1);
+-	byte = 0x09;
+-	i2c_write(0x4B, 0x79, 1, &byte, 1);
+-
+-	udelay(5000);
+-#endif
++	print_cpuinfo();
++	printf("Board revision: %d\n", get_board_revision());
+ 	return 0;
+ }
+ 
+@@ -616,6 +851,10 @@
+ 
+ #endif
+ 
++	/* Enable GPIO 4, 5, & 6 clocks */
++	sr32(CM_FCLKEN_PER, 17, 3, 0x7);
++	sr32(CM_ICLKEN_PER, 17, 3, 0x7);
++
+ #ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ 	/* Turn on all 3 I2C clocks */
+ 	sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
+@@ -638,10 +877,6 @@
+ 	sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
+ 	sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
+ 
+-	/* Enable GPIO5 clocks for blinky LEDs */
+-	sr32(CM_FCLKEN_PER, 16, 1, 0x1);	/* FCKen GPIO5 */
+-	sr32(CM_ICLKEN_PER, 16, 1, 0x1);	/* ICKen GPIO5 */
+-
+ 	delay(1000);
+ }
+ 
+@@ -748,6 +983,11 @@
+ 	MUX_VAL(CP(DSS_DATA19),     (IEN  | PTD | DIS | M4)) /*GPIO_89*/\
+ 	MUX_VAL(CP(DSS_DATA20),     (IEN  | PTD | DIS | M4)) /*GPIO_90*/\
+ 	MUX_VAL(CP(DSS_DATA21),     (IEN  | PTD | DIS | M4)) /*GPIO_91*/\
++	MUX_VAL(CP(CSI2_DX0),       (IEN  | PTD | EN  | M4)) /*GPIO_112*/\
++	MUX_VAL(CP(CSI2_DY0),       (IEN  | PTD | EN  | M4)) /*GPIO_113*/\
++	MUX_VAL(CP(CSI2_DX1),       (IEN  | PTD | EN  | M4)) /*GPIO_114*/\
++								 /* - PEN_DOWN*/\
++	MUX_VAL(CP(CSI2_DY1),       (IEN  | PTD | EN  | M4)) /*GPIO_115*/\
+ 	MUX_VAL(CP(CAM_WEN),        (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
+ 	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
+ 	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
+@@ -755,10 +995,12 @@
+ 	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
+ 	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
+ 	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
+-	MUX_VAL(CP(MMC1_DAT4),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
+-	MUX_VAL(CP(MMC1_DAT5),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
+-	MUX_VAL(CP(MMC1_DAT6),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
+-	MUX_VAL(CP(MMC1_DAT7),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
++	MUX_VAL(CP(MMC1_DAT4),      (IEN  | PTD | EN  | M4)) /*GPIO_126*/\
++	MUX_VAL(CP(MMC1_DAT5),      (IEN  | PTD | EN  | M4)) /*GPIO_127*/\
++	MUX_VAL(CP(MMC1_DAT6),      (IEN  | PTD | EN  | M4)) /*GPIO_128*/\
++	MUX_VAL(CP(MMC1_DAT7),      (IEN  | PTD | EN  | M4)) /*GPIO_129*/\
++	MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
++	MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
+ 	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
+ 	MUX_VAL(CP(UART1_RTS),      (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
+ 	MUX_VAL(CP(UART1_CTS),      (IEN  | PTU | DIS | M0)) /*UART1_CTS*/\
+@@ -833,6 +1075,7 @@
+ 	__raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
+ 	delay(1000);
+ 
++#ifdef CFG_NAND_K9F1G08R0A
+ 	if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
+ 		__raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ 		__raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+@@ -853,9 +1096,10 @@
+ #endif
+ 			return 1;
+ 		}
+-
+ 	}
++#endif
+ 
++#ifdef CFG_ONENAND
+ 	if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
+ 		__raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
+ 		__raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
+@@ -877,6 +1121,8 @@
+ 			return 1;
+ 		}
+ 	}
++#endif
++
+ 	return 0;
+ }
+ 
+diff -uNr x-load-f243938.orig/common/cmd_load.c x-load-f243938/common/cmd_load.c
+--- x-load-f243938.orig/common/cmd_load.c	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/common/cmd_load.c	2012-06-07 15:20:05.921695819 -0300
+@@ -26,7 +26,7 @@
+  */
+ #include <common.h>
+ 
+-#define putc serial_putc
++#define putc 
+ #define tstc serial_tstc
+ 
+ /*******************************************************
+diff -uNr x-load-f243938.orig/cpu/omap4/config.mk x-load-f243938/cpu/omap4/config.mk
+--- x-load-f243938.orig/cpu/omap4/config.mk	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/cpu/omap4/config.mk	2012-06-07 14:45:39.449648667 -0300
+@@ -0,0 +1,32 @@
++#
++# (C) Copyright 2002
++# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License
++# version 2 as published by the Free Software Foundation.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
++	-msoft-float
++
++PLATFORM_CPPFLAGS += -march=armv7-a
++# =========================================================================
++#
++# Supply options according to compiler version
++#
++# =========================================================================
++PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
++PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
+diff -uNr x-load-f243938.orig/cpu/omap4/cpu.c x-load-f243938/cpu/omap4/cpu.c
+--- x-load-f243938.orig/cpu/omap4/cpu.c	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/cpu/omap4/cpu.c	2012-06-07 14:45:39.449648667 -0300
+@@ -0,0 +1,79 @@
++/*
++ * (C) Copyright 2004-2009 Texas Insturments
++ *
++ * (C) Copyright 2002
++ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
++ * Marius Groeger <mgroeger@sysgo.de>
++ *
++ * (C) Copyright 2002
++ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++/*
++ * CPU specific code
++ */
++
++#include <common.h>
++#include <asm/io.h>
++
++/* See also ARM Ref. Man. */
++#define C1_MMU		(1<<0)		/* mmu off/on */
++#define C1_ALIGN	(1<<1)		/* alignment faults off/on */
++#define C1_DC		(1<<2)		/* dcache off/on */
++#define C1_WB		(1<<3)		/* merging write buffer on/off */
++#define C1_BIG_ENDIAN	(1<<7)		/* big endian off/on */
++#define C1_SYS_PROT	(1<<8)		/* system protection */
++#define C1_ROM_PROT	(1<<9)		/* ROM protection */
++#define C1_IC		(1<<12)		/* icache off/on */
++#define C1_HIGH_VECTORS	(1<<13) /* location of vectors: low/high addresses */
++#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
++
++int cpu_init (void)
++{
++	return 0;
++}
++
++unsigned int cortex_a9_rev(void)
++{
++
++	unsigned int i;
++
++	/* turn off I/D-cache */
++	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (i));
++
++	return i;
++}
++
++unsigned int omap_revision(void)
++{
++	unsigned int rev = cortex_a9_rev();
++
++	switch(rev) {
++	case 0x410FC091:
++		return OMAP4430_ES1_0;
++	case 0x411FC092:
++		if (__raw_readl(0x4a002204) == 0x3b95c02f)
++			return OMAP4430_ES2_1;
++		else
++			return OMAP4430_ES2_0;
++	default:
++		return OMAP4430_SILICON_ID_INVALID;
++	}
++}
+diff -uNr x-load-f243938.orig/cpu/omap4/Makefile x-load-f243938/cpu/omap4/Makefile
+--- x-load-f243938.orig/cpu/omap4/Makefile	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/cpu/omap4/Makefile	2012-06-07 14:45:39.449648667 -0300
+@@ -0,0 +1,44 @@
++#
++# (C) Copyright 2009
++# Texas Instruments, <www.ti.com>
++# (C) Copyright 2000-2003
++# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License
++# version 2 as published by the Free Software Foundation.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= lib$(CPU).a
++
++START	= start.o
++OBJS	= cpu.o mmc.o sys_info.o
++
++all:	.depend $(START) $(LIB)
++
++$(LIB):	$(OBJS)
++	$(AR) crv $@ $(OBJS)
++
++#########################################################################
++
++.depend:	Makefile $(START:.o=.S) $(OBJS:.o=.c)
++		$(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
++
++sinclude .depend
++
++#########################################################################
+diff -uNr x-load-f243938.orig/cpu/omap4/mmc.c x-load-f243938/cpu/omap4/mmc.c
+--- x-load-f243938.orig/cpu/omap4/mmc.c	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/cpu/omap4/mmc.c	2012-06-07 14:45:39.449648667 -0300
+@@ -0,0 +1,547 @@
++/*
++ * (C) Copyright 2008
++ * Texas Instruments, <www.ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation's version 2 of
++ * the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#include <common.h>
++#include <part.h>
++#include <fat.h>
++#include <mmc.h>
++#include <i2c.h>
++
++const unsigned short mmc_transspeed_val[15][4] = {
++	{CLKD(10, 1), CLKD(10, 10), CLKD(10, 100), CLKD(10, 1000)},
++	{CLKD(12, 1), CLKD(12, 10), CLKD(12, 100), CLKD(12, 1000)},
++	{CLKD(13, 1), CLKD(13, 10), CLKD(13, 100), CLKD(13, 1000)},
++	{CLKD(15, 1), CLKD(15, 10), CLKD(15, 100), CLKD(15, 1000)},
++	{CLKD(20, 1), CLKD(20, 10), CLKD(20, 100), CLKD(20, 1000)},
++	{CLKD(26, 1), CLKD(26, 10), CLKD(26, 100), CLKD(26, 1000)},
++	{CLKD(30, 1), CLKD(30, 10), CLKD(30, 100), CLKD(30, 1000)},
++	{CLKD(35, 1), CLKD(35, 10), CLKD(35, 100), CLKD(35, 1000)},
++	{CLKD(40, 1), CLKD(40, 10), CLKD(40, 100), CLKD(40, 1000)},
++	{CLKD(45, 1), CLKD(45, 10), CLKD(45, 100), CLKD(45, 1000)},
++	{CLKD(52, 1), CLKD(52, 10), CLKD(52, 100), CLKD(52, 1000)},
++	{CLKD(55, 1), CLKD(55, 10), CLKD(55, 100), CLKD(55, 1000)},
++	{CLKD(60, 1), CLKD(60, 10), CLKD(60, 100), CLKD(60, 1000)},
++	{CLKD(70, 1), CLKD(70, 10), CLKD(70, 100), CLKD(70, 1000)},
++	{CLKD(80, 1), CLKD(80, 10), CLKD(80, 100), CLKD(80, 1000)}
++};
++
++mmc_card_data cur_card_data;
++static block_dev_desc_t mmc_blk_dev;
++
++block_dev_desc_t *mmc_get_dev(int dev)
++{
++	return ((block_dev_desc_t *) &mmc_blk_dev);
++}
++
++unsigned char mmc_board_init(void)
++{
++	unsigned int value = 0;
++
++	return 1;
++}
++
++void mmc_init_stream(void)
++{
++	volatile unsigned int mmc_stat;
++
++	OMAP_HSMMC_CON |= INIT_INITSTREAM;
++
++	OMAP_HSMMC_CMD = MMC_CMD0;
++	do {
++		mmc_stat = OMAP_HSMMC_STAT;
++	} while (!(mmc_stat & CC_MASK));
++
++	OMAP_HSMMC_STAT = CC_MASK;
++
++	OMAP_HSMMC_CMD = MMC_CMD0;
++	do {
++		mmc_stat = OMAP_HSMMC_STAT;
++	} while (!(mmc_stat & CC_MASK));
++
++	OMAP_HSMMC_STAT = OMAP_HSMMC_STAT;
++	OMAP_HSMMC_CON &= ~INIT_INITSTREAM;
++}
++
++unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div)
++{
++	unsigned int val;
++
++	mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK),
++		    (ICE_STOP | DTO_15THDTO | CEN_DISABLE));
++
++	switch (iclk) {
++	case CLK_INITSEQ:
++		val = MMC_INIT_SEQ_CLK / 2;
++		break;
++	case CLK_400KHZ:
++		val = MMC_400kHz_CLK;
++		break;
++	case CLK_MISC:
++		val = clk_div;
++		break;
++	default:
++		return 0;
++	}
++	mmc_reg_out(OMAP_HSMMC_SYSCTL,
++		    ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE);
++
++	while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) {
++	}
++
++	OMAP_HSMMC_SYSCTL |= CEN_ENABLE;
++	return 1;
++}
++
++unsigned char mmc_init_setup(void)
++{
++	unsigned int reg_val;
++
++	mmc_board_init();
++
++	OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET;
++	while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ;
++
++	OMAP_HSMMC_SYSCTL |= SOFTRESETALL;
++	while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ;
++
++	OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0;
++	OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP;
++
++	reg_val = OMAP_HSMMC_CON & RESERVED_MASK;
++
++	OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH |
++	    CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC |
++	    STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN;
++
++	mmc_clock_config(CLK_INITSEQ, 0);
++	OMAP_HSMMC_HCTL |= SDBP_PWRON;
++
++	OMAP_HSMMC_IE = 0x307f0033;
++
++	mmc_init_stream();
++	return 1;
++}
++
++unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg,
++			   unsigned int *response)
++{
++	volatile unsigned int mmc_stat;
++
++	while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) {
++	}
++
++	OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT;
++	OMAP_HSMMC_STAT = 0xFFFFFFFF;
++	OMAP_HSMMC_ARG = arg;
++	OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK |
++	    CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE |
++	    DE_DISABLE;
++
++	while (1) {
++		do {
++			mmc_stat = OMAP_HSMMC_STAT;
++		} while (mmc_stat == 0);
++
++		if ((mmc_stat & ERRI_MASK) != 0)
++			return (unsigned char) mmc_stat;
++
++		if (mmc_stat & CC_MASK) {
++			OMAP_HSMMC_STAT = CC_MASK;
++			response[0] = OMAP_HSMMC_RSP10;
++			if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) {
++				response[1] = OMAP_HSMMC_RSP32;
++				response[2] = OMAP_HSMMC_RSP54;
++				response[3] = OMAP_HSMMC_RSP76;
++			}
++			break;
++		}
++	}
++	return 1;
++}
++
++unsigned char mmc_read_data(unsigned int *output_buf)
++{
++	volatile unsigned int mmc_stat;
++	unsigned int read_count = 0;
++
++	/*
++	 * Start Polled Read
++	 */
++	while (1) {
++		do {
++			mmc_stat = OMAP_HSMMC_STAT;
++		} while (mmc_stat == 0);
++
++		if ((mmc_stat & ERRI_MASK) != 0)
++			return (unsigned char) mmc_stat;
++
++		if (mmc_stat & BRR_MASK) {
++			unsigned int k;
++
++			OMAP_HSMMC_STAT |= BRR_MASK;
++			for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) {
++				*output_buf = OMAP_HSMMC_DATA;
++				output_buf++;
++				read_count += 4;
++			}
++		}
++
++		if (mmc_stat & BWR_MASK)
++			OMAP_HSMMC_STAT |= BWR_MASK;
++
++		if (mmc_stat & TC_MASK) {
++			OMAP_HSMMC_STAT |= TC_MASK;
++			break;
++		}
++	}
++	return 1;
++}
++
++unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur)
++{
++	unsigned char err;
++	unsigned int argument = 0;
++	unsigned int ocr_value, ocr_recvd, ret_cmd41, hcs_val;
++	unsigned int resp[4];
++	unsigned short retry_cnt = 2000;
++
++	/* Set to Initialization Clock */
++	err = mmc_clock_config(CLK_400KHZ, 0);
++	if (err != 1)
++		return err;
++
++	mmc_card_cur->RCA = MMC_RELATIVE_CARD_ADDRESS;
++	argument = 0x00000000;
++
++	ocr_value = (0x1FF << 15);
++	err = mmc_send_cmd(MMC_CMD0, argument, resp);
++	if (err != 1)
++		return err;
++
++	argument = SD_CMD8_CHECK_PATTERN | SD_CMD8_2_7_3_6_V_RANGE;
++	err = mmc_send_cmd(MMC_SDCMD8, argument, resp);
++	hcs_val = (err == 1) ?
++	    MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR :
++	    MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE;
++
++	argument = 0x0000 << 16;
++	err = mmc_send_cmd(MMC_CMD55, argument, resp);
++	if (err == 1) {
++		mmc_card_cur->card_type = SD_CARD;
++		ocr_value |= hcs_val;
++		ret_cmd41 = MMC_ACMD41;
++	} else {
++		mmc_card_cur->card_type = MMC_CARD;
++		ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR;
++		ret_cmd41 = MMC_CMD1;
++		OMAP_HSMMC_CON &= ~OD;
++		OMAP_HSMMC_CON |= OPENDRAIN;
++	}
++
++	argument = ocr_value;
++	err = mmc_send_cmd(ret_cmd41, argument, resp);
++	if (err != 1)
++		return err;
++
++	ocr_recvd = ((mmc_resp_r3 *) resp)->ocr;
++
++	while (!(ocr_recvd & (0x1 << 31)) && (retry_cnt > 0)) {
++		retry_cnt--;
++		if (mmc_card_cur->card_type == SD_CARD) {
++			argument = 0x0000 << 16;
++			err = mmc_send_cmd(MMC_CMD55, argument, resp);
++		}
++
++		argument = ocr_value;
++		err = mmc_send_cmd(ret_cmd41, argument, resp);
++		if (err != 1)
++			return err;
++		ocr_recvd = ((mmc_resp_r3 *) resp)->ocr;
++	}
++
++	if (!(ocr_recvd & (0x1 << 31)))
++		return 0;
++
++	if (mmc_card_cur->card_type == MMC_CARD) {
++		if ((ocr_recvd & MMC_OCR_REG_ACCESS_MODE_MASK) ==
++		    MMC_OCR_REG_ACCESS_MODE_SECTOR) {
++			mmc_card_cur->mode = SECTOR_MODE;
++		} else {
++			mmc_card_cur->mode = BYTE_MODE;
++		}
++
++		ocr_recvd &= ~MMC_OCR_REG_ACCESS_MODE_MASK;
++	} else {
++		if ((ocr_recvd & MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK)
++		    == MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR) {
++			mmc_card_cur->mode = SECTOR_MODE;
++		} else {
++			mmc_card_cur->mode = BYTE_MODE;
++		}
++		ocr_recvd &= ~MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK;
++	}
++
++	ocr_recvd &= ~(0x1 << 31);
++	if (!(ocr_recvd & ocr_value))
++		return 0;
++
++	err = mmc_send_cmd(MMC_CMD2, argument, resp);
++	if (err != 1)
++		return err;
++
++	if (mmc_card_cur->card_type == MMC_CARD) {
++		argument = mmc_card_cur->RCA << 16;
++		err = mmc_send_cmd(MMC_CMD3, argument, resp);
++		if (err != 1)
++			return err;
++	} else {
++		argument = 0x00000000;
++		err = mmc_send_cmd(MMC_SDCMD3, argument, resp);
++		if (err != 1)
++			return err;
++
++		mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca;
++	}
++
++	OMAP_HSMMC_CON &= ~OD;
++	OMAP_HSMMC_CON |= NOOPENDRAIN;
++	return 1;
++}
++
++unsigned char mmc_read_cardsize(mmc_card_data *mmc_dev_data,
++				mmc_csd_reg_t *cur_csd)
++{
++	mmc_extended_csd_reg_t ext_csd;
++	unsigned int size, count, blk_len, blk_no, card_size, argument;
++	unsigned char err;
++	unsigned int resp[4];
++
++	if (mmc_dev_data->mode == SECTOR_MODE) {
++		if (mmc_dev_data->card_type == SD_CARD) {
++			card_size =
++			    (((mmc_sd2_csd_reg_t *) cur_csd)->
++			     c_size_lsb & MMC_SD2_CSD_C_SIZE_LSB_MASK) |
++			    ((((mmc_sd2_csd_reg_t *) cur_csd)->
++			      c_size_msb & MMC_SD2_CSD_C_SIZE_MSB_MASK)
++			     << MMC_SD2_CSD_C_SIZE_MSB_OFFSET);
++			mmc_dev_data->size = card_size * 1024;
++			if (mmc_dev_data->size == 0)
++				return 0;
++		} else {
++			argument = 0x00000000;
++			err = mmc_send_cmd(MMC_CMD8, argument, resp);
++			if (err != 1)
++				return err;
++			err = mmc_read_data((unsigned int *) &ext_csd);
++			if (err != 1)
++				return err;
++			mmc_dev_data->size = ext_csd.sectorcount;
++
++			if (mmc_dev_data->size == 0)
++				mmc_dev_data->size = 8388608;
++		}
++	} else {
++		if (cur_csd->c_size_mult >= 8)
++			return 0;
++
++		if (cur_csd->read_bl_len >= 12)
++			return 0;
++
++		/* Compute size */
++		count = 1 << (cur_csd->c_size_mult + 2);
++		card_size = (cur_csd->c_size_lsb & MMC_CSD_C_SIZE_LSB_MASK) |
++		    ((cur_csd->c_size_msb & MMC_CSD_C_SIZE_MSB_MASK)
++		     << MMC_CSD_C_SIZE_MSB_OFFSET);
++		blk_no = (card_size + 1) * count;
++		blk_len = 1 << cur_csd->read_bl_len;
++		size = blk_no * blk_len;
++		mmc_dev_data->size = size / MMCSD_SECTOR_SIZE;
++		if (mmc_dev_data->size == 0)
++			return 0;
++	}
++	return 1;
++}
++
++unsigned char omap_mmc_read_sect(unsigned int start_sec, unsigned int num_bytes,
++				 mmc_card_data *mmc_c,
++				 unsigned long *output_buf)
++{
++	unsigned char err;
++	unsigned int argument;
++	unsigned int resp[4];
++	unsigned int num_sec_val =
++	    (num_bytes + (MMCSD_SECTOR_SIZE - 1)) / MMCSD_SECTOR_SIZE;
++	unsigned int sec_inc_val;
++
++	if (num_sec_val == 0)
++		return 1;
++
++	if (mmc_c->mode == SECTOR_MODE) {
++		argument = start_sec;
++		sec_inc_val = 1;
++	} else {
++		argument = start_sec * MMCSD_SECTOR_SIZE;
++		sec_inc_val = MMCSD_SECTOR_SIZE;
++	}
++
++	while (num_sec_val) {
++		err = mmc_send_cmd(MMC_CMD17, argument, resp);
++		if (err != 1)
++			return err;
++
++		err = mmc_read_data((unsigned int *) output_buf);
++		if (err != 1)
++			return err;
++
++		output_buf += (MMCSD_SECTOR_SIZE / 4);
++		argument += sec_inc_val;
++		num_sec_val--;
++	}
++	return 1;
++}
++
++unsigned char configure_mmc(mmc_card_data *mmc_card_cur)
++{
++	unsigned char ret_val;
++	unsigned int argument;
++	unsigned int resp[4];
++	unsigned int trans_clk, trans_fact, trans_unit, retries = 2;
++	mmc_csd_reg_t Card_CSD;
++	unsigned char trans_speed;
++
++	ret_val = mmc_init_setup();
++
++	if (ret_val != 1)
++		return ret_val;
++
++	do {
++		ret_val = mmc_detect_card(mmc_card_cur);
++		retries--;
++	} while ((retries > 0) && (ret_val != 1));
++
++	argument = mmc_card_cur->RCA << 16;
++	ret_val = mmc_send_cmd(MMC_CMD9, argument, resp);
++	if (ret_val != 1)
++		return ret_val;
++
++	((unsigned int *) &Card_CSD)[3] = resp[3];
++	((unsigned int *) &Card_CSD)[2] = resp[2];
++	((unsigned int *) &Card_CSD)[1] = resp[1];
++	((unsigned int *) &Card_CSD)[0] = resp[0];
++
++	if (mmc_card_cur->card_type == MMC_CARD)
++		mmc_card_cur->version = Card_CSD.spec_vers;
++
++	trans_speed = Card_CSD.tran_speed;
++
++	ret_val = mmc_send_cmd(MMC_CMD4, MMC_DSR_DEFAULT << 16, resp);
++	if (ret_val != 1)
++		return ret_val;
++
++	trans_unit = trans_speed & MMC_CSD_TRAN_SPEED_UNIT_MASK;
++	trans_fact = trans_speed & MMC_CSD_TRAN_SPEED_FACTOR_MASK;
++
++	if (trans_unit > MMC_CSD_TRAN_SPEED_UNIT_100MHZ)
++		return 0;
++
++	if ((trans_fact < MMC_CSD_TRAN_SPEED_FACTOR_1_0) ||
++	    (trans_fact > MMC_CSD_TRAN_SPEED_FACTOR_8_0))
++		return 0;
++
++	trans_unit >>= 0;
++	trans_fact >>= 3;
++
++	trans_clk = mmc_transspeed_val[trans_fact - 1][trans_unit] * 2;
++	ret_val = mmc_clock_config(CLK_MISC, trans_clk);
++
++	if (ret_val != 1)
++		return ret_val;
++
++	argument = mmc_card_cur->RCA << 16;
++	ret_val = mmc_send_cmd(MMC_CMD7_SELECT, argument, resp);
++	if (ret_val != 1)
++		return ret_val;
++
++	/* Configure the block length to 512 bytes */
++	argument = MMCSD_SECTOR_SIZE;
++	ret_val = mmc_send_cmd(MMC_CMD16, argument, resp);
++	if (ret_val != 1)
++		return ret_val;
++
++	/* get the card size in sectors */
++	ret_val = mmc_read_cardsize(mmc_card_cur, &Card_CSD);
++	if (ret_val != 1)
++		return ret_val;
++
++	return 1;
++}
++unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt,
++			void *dst)
++{
++	omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data,
++			   (unsigned long *) dst);
++	return 1;
++}
++
++int mmc_init(int verbose)
++{
++	unsigned char ret;
++
++	ret = configure_mmc(&cur_card_data);
++
++	if (ret == 1) {
++		mmc_blk_dev.if_type = IF_TYPE_MMC;
++		mmc_blk_dev.part_type = PART_TYPE_DOS;
++		mmc_blk_dev.dev = 0;
++		mmc_blk_dev.lun = 0;
++		mmc_blk_dev.type = 0;
++
++		/* FIXME fill in the correct size (is set to 32MByte) */
++		mmc_blk_dev.blksz = MMCSD_SECTOR_SIZE;
++		mmc_blk_dev.lba = 0x10000;
++		mmc_blk_dev.removable = 0;
++		mmc_blk_dev.block_read = mmc_bread;
++
++		fat_register_device(&mmc_blk_dev, 1);
++		return 1;
++	}
++	else 
++		return 0;
++}
++
++int mmc_read(ulong src, uchar *dst, int size)
++{
++	return 0;
++}
++
++int mmc_write(uchar *src, ulong dst, int size)
++{
++	return 0;
++}
++
++int mmc2info(ulong addr)
++{
++	return 0;
++}
+diff -uNr x-load-f243938.orig/cpu/omap4/start.S x-load-f243938/cpu/omap4/start.S
+--- x-load-f243938.orig/cpu/omap4/start.S	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/cpu/omap4/start.S	2012-06-07 14:45:39.449648667 -0300
+@@ -0,0 +1,220 @@
++/*
++ *  armboot - Startup Code for OMAP4430/ARM Cortex CPU-core
++ *
++ *  Copyright (c) 2004	Texas Instruments <r-woodruff2@ti.com>
++ *
++ *  Copyright (c) 2001	Marius Groger <mag@sysgo.de>
++ *  Copyright (c) 2002	Alex Zupke <azu@sysgo.de>
++ *  Copyright (c) 2002	Gary Jennejohn <gj@denx.de>
++ *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
++ *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
++ *  Copyright (c) 2006	Syed Mohammed Khasim <x0khasim@ti.com>
++ *  Copyright (c) 2009	Texas Instruments
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <config.h>
++#if !defined(CONFIG_INTEGRATOR) && ! defined(CONFIG_ARCH_CINTEGRATOR)
++#include <asm/arch/cpu.h>
++#endif
++#define CONFIG_SKIP_RELOCATE_XLOADER
++.globl _start
++_start:
++	b	reset
++ 	ldr	pc, _hang
++	ldr	pc, _hang
++	ldr	pc, _hang
++	ldr	pc, _hang
++	ldr	pc, _hang
++	ldr	pc, _hang
++	ldr	pc, _hang
++
++_hang:
++ 	.word do_hang
++	
++	.word 0x12345678
++	.word 0x12345678
++	.word 0x12345678
++	.word 0x12345678
++	.word 0x12345678
++	.word 0x12345678
++	.word 0x12345678 /* now 16*4=64 */
++
++.global _end_vect
++_end_vect:
++
++	.balignl 16,0xdeadbeef
++/*
++ *************************************************************************
++ *
++ * Startup Code (reset vector)
++ *
++ * do important init only if we don't start from memory!
++ * setup Memory and board specific bits prior to relocation.
++ * relocate armboot to ram
++ * setup stack
++ *
++ *************************************************************************
++ */
++
++_TEXT_BASE:
++	.word	TEXT_BASE
++
++.globl _armboot_start
++_armboot_start:
++	.word _start
++
++/*
++ * These are defined in the board-specific linker script.
++ */
++.globl _bss_start
++_bss_start:
++	.word __bss_start
++
++.globl _bss_end
++_bss_end:
++	.word _end
++
++/*
++ * the actual reset code
++ */
++
++reset:
++	/* Use a temp scratch pad memory
++	 * to store the boot reason
++	 */
++	ldr     r4, scratchpad
++	ldr     r5, [r0, #0x8]          /* r5 <- value of boot device */
++	str     r5, [r4]                /* store r5 in scratchpad reg */
++
++	/*
++	 * set the cpu to SVC32 mode
++	 */
++	mrs	r0,cpsr
++	bic	r0,r0,#0x1f
++	orr	r0,r0,#0xd3
++	msr	cpsr,r0
++
++       /* Copy vectors to mask ROM indirect addr */
++	adr	r0, _start		/* r0 <- current position of code   */
++        add     r0, r0, #4				/* skip reset vector */
++	mov	r2, #64			/* r2 <- size to copy  */
++	add	r2, r0, r2		/* r2 <- source end address	    */
++	mov	r1, #SRAM_OFFSET0	  /* build vect addr */
++	mov	r3, #SRAM_OFFSET1
++	add	r1, r1, r3
++	mov	r3, #SRAM_OFFSET2
++	add	r1, r1, r3
++next:
++	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
++	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
++	cmp	r0, r2			/* until source end address [r2]    */
++	bne	next			/* loop until equal */
++	/* the mask ROM code should have PLL and others stable */
++	bl  cpu_init_crit
++
++#ifndef CONFIG_SKIP_RELOCATE_XLOADER
++relocate:				/* relocate U-Boot to RAM	    */
++	adr	r0, _start		/* r0 <- current position of code   */
++	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
++	cmp	r0, r1			/* don't reloc during debug	    */
++	beq	stack_setup
++
++	ldr	r2, _armboot_start
++	ldr	r3, _bss_start
++	sub	r2, r3, r2		/* r2 <- size of armboot	    */
++	add	r2, r0, r2		/* r2 <- source end address	    */
++
++copy_loop:                              /* copy 32 bytes at a time          */
++	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
++	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
++	cmp	r0, r2			/* until source end addreee [r2]    */
++	ble	copy_loop
++#endif
++
++	/* Set up the stack						    */
++stack_setup:
++	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
++	and	sp, sp, #~7		/* 8 byte alinged for (ldr/str)d    */
++
++	/* Clear BSS (if any).  Is below tx (watch load addr - need space)  */
++clear_bss:
++	ldr	r0, _bss_start		/* find start of bss segment        */
++	ldr	r1, _bss_end		/* stop here                        */
++	mov 	r2, #0x00000000		/* clear value                      */
++clbss_l:
++	str	r2, [r0]		/* clear BSS location               */
++	cmp	r0, r1			/* are we at the end yet            */
++	add	r0, r0, #4		/* increment clear index pointer    */
++	bne	clbss_l                 /* keep clearing till at end        */
++
++	ldr	pc, _start_armboot	/* jump to C code                   */
++
++_start_armboot: .word start_armboot
++
++
++/*
++ *************************************************************************
++ *
++ * CPU_init_critical registers
++ *
++ * setup important registers
++ * setup memory timing
++ *
++ *************************************************************************
++ */
++cpu_init_crit:
++	/*
++	 * Invalidate L1 I/D
++	 */
++        mov	r0, #0                 /* set up for MCR */
++        mcr	p15, 0, r0, c8, c7, 0  /* invalidate TLBs */
++        mcr	p15, 0, r0, c7, c5, 0  /* invalidate icache */
++
++	/*
++	 * disable MMU stuff and caches
++	 */
++	mrc	p15, 0, r0, c1, c0, 0
++	bic	r0, r0, #0x00002000	@ clear bits 13 (--V-)
++	bic	r0, r0, #0x00000007	@ clear bits 2:0 (-CAM)
++	orr	r0, r0, #0x00000002	@ set bit 1 (--A-) Align
++	orr	r0, r0, #0x00000800	@ set bit 12 (Z---) BTB
++	mcr	p15, 0, r0, c1, c0, 0
++
++	/*
++	 * Jump to board specific initialization... The Mask ROM will
++         * have already initialized basic memory.  Go here to bump up
++         * clock rate and handle wake up conditions.
++	 */
++	mov	ip, lr		/* persevere link reg across call */
++	bl	lowlevel_init	/* go setup pll,mux,memory */
++	mov	lr, ip		/* restore link */
++	mov	pc, lr		/* back to my caller */
++
++
++/*
++ * exception handler
++ */
++ 	.align  5
++do_hang:
++	ldr	sp, _TEXT_BASE		/* use 32 words abort stack */
++   	bl	hang			/* hang and never return */
++
++scratchpad:
++    .word 0x4A326000
+diff -uNr x-load-f243938.orig/cpu/omap4/sys_info.c x-load-f243938/cpu/omap4/sys_info.c
+--- x-load-f243938.orig/cpu/omap4/sys_info.c	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/cpu/omap4/sys_info.c	2012-06-07 14:45:39.449648667 -0300
+@@ -0,0 +1,35 @@
++/*
++ * (C) Copyright 2004-2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/sys_info.h>
++
++
++/******************************************
++ * get_cpu_rev(void) - extract version info
++ ******************************************/
++u32 get_cpu_rev(void)
++{
++	return CPU_4430_ES1;
++
++}
++
++
+diff -uNr x-load-f243938.orig/drivers/k9f1g08r0a.c x-load-f243938/drivers/k9f1g08r0a.c
+--- x-load-f243938.orig/drivers/k9f1g08r0a.c	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/drivers/k9f1g08r0a.c	2012-06-07 14:45:39.453648667 -0300
+@@ -42,6 +42,7 @@
+  */
+ #define MT29F1G_MFR		0x2c  /* Micron */
+ #define MT29F1G_MFR2		0x20  /* numonyx */
++#define MT29F1G_MFR3		0xad  /* Hynix */
+ #define MT29F1G_ID		0xa1  /* x8, 1GiB */
+ #define MT29F2G_ID      	0xba  /* x16, 2GiB */
+ #define MT29F4G_ID		0xbc  /* x16, 4GiB */
+@@ -206,13 +207,18 @@
+ 
+ 	NAND_DISABLE_CE();
+ 
+-	if (((mfr == MT29F1G_MFR || mfr == MT29F1G_MFR2) &&
++	if (((mfr == MT29F1G_MFR || mfr == MT29F1G_MFR2 || mfr == MT29F1G_MFR3) &&
+ 		(id == MT29F1G_ID || id == MT29F2G_ID || id == MT29F4G_ID)) ||
+ 	     (mfr == K9F1G08R0A_MFR && (id == K9F1G08R0A_ID))) {
+ 		return 0;
+ 	} else {
+-		printf("Unknown chip: mfr was 0x%02x, id was 0x%02x\n", mfr, id);
+-		return 1;
++		if ((mfr == 0) && (id == 0)) {
++			printf("No NAND detected\n");
++			return 0;
++		} else {
++			printf("Unknown chip: mfr was 0x%02x, id was 0x%02x\n", mfr, id);
++			return 1;
++		}
+ 	}
+ }
+ 
+diff -uNr x-load-f243938.orig/drivers/Makefile x-load-f243938/drivers/Makefile
+--- x-load-f243938.orig/drivers/Makefile	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/drivers/Makefile	2012-06-07 14:45:39.449648667 -0300
+@@ -26,7 +26,7 @@
+ # CFLAGS += -DET_DEBUG -DDEBUG
+ 
+ LIB	= libdrivers.a
+-OBJS	= serial.o ns16550.o onenand.o omap24xx_i2c.o
++OBJS	= serial.o ns16550.o omap24xx_i2c.o
+ 
+ ifeq ($(BOARD), omap3430sdp)
+ OBJS 	+= k9f1g08r0a.o
+@@ -41,7 +41,7 @@
+ endif
+ 
+ ifeq ($(BOARD), omap3evm)
+-OBJS 	+= k9f1g08r0a.o
++OBJS 	+= k9f1g08r0a.o onenand.o
+ endif
+ 
+ ifeq ($(BOARD), overo)
+diff -uNr x-load-f243938.orig/fs/fat/fat.c x-load-f243938/fs/fat/fat.c
+--- x-load-f243938.orig/fs/fat/fat.c	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/fs/fat/fat.c	2012-06-07 14:45:39.453648667 -0300
+@@ -384,7 +384,7 @@
+ 			newclust = get_fatent(mydata, endclust);
+ 			if((newclust -1)!=endclust)
+ 				goto getit;
+-			if (newclust <= 0x0001 || newclust >= 0xfff0) {
++			if (newclust <= 0x0001 || newclust >= 0xfffff0) {
+ 				FAT_DPRINT("curclust: 0x%x\n", newclust);
+ 				FAT_DPRINT("Invalid FAT entry\n");
+ 				return gotsize;
+@@ -419,7 +419,7 @@
+ 		filesize -= actsize;
+ 		buffer += actsize;
+ 		curclust = get_fatent(mydata, endclust);
+-		if (curclust <= 0x0001 || curclust >= 0xfff0) {
++		if (curclust <= 0x0001 || curclust >= 0xfffff0) {
+ 			FAT_DPRINT("curclust: 0x%x\n", curclust);
+ 			FAT_ERROR("Invalid FAT entry\n");
+ 			return gotsize;
+@@ -580,7 +580,7 @@
+ 	    return retdent;
+ 	}
+ 	curclust = get_fatent (mydata, curclust);
+-	if (curclust <= 0x0001 || curclust >= 0xfff0) {
++	if (curclust <= 0x0001 || curclust >= 0xfffff0) {
+ 	    FAT_DPRINT ("curclust: 0x%x\n", curclust);
+ 	    FAT_ERROR ("Invalid FAT entry\n");
+ 	    return NULL;
+@@ -679,7 +679,7 @@
+     dir_entry *dentptr;
+     __u16 prevcksum = 0xffff;
+     char *subname = "";
+-    int rootdir_size, cursect;
++    int rootdir_size, cursect, curclus;
+     int idx, isdir = 0;
+     int files = 0, dirs = 0;
+     long ret = 0;
+@@ -697,6 +697,7 @@
+     mydata->fat_sect = bs.reserved;
+     cursect = mydata->rootdir_sect
+ 	    = mydata->fat_sect + mydata->fatlength * bs.fats;
++    curclus = bs.root_cluster;   // For FAT32 only
+     mydata->clust_size = bs.cluster_size;
+     if (mydata->fatsize == 32) {
+ 	rootdir_size = mydata->clust_size;
+@@ -818,7 +819,16 @@
+ 
+ 	    goto rootdir_done;  /* We got a match */
+ 	}
+-	cursect++;
++
++	if (mydata->fatsize != 32)
++	   cursect++;
++	else {
++	   // FAT32 does not guarantee contiguous root directory
++	   curclus = get_fatent (mydata, curclus);
++	   cursect = (curclus * mydata->clust_size) + mydata->data_begin;
++
++	   FAT_DPRINT ("root clus %d sector %d\n", curclus, cursect);
++	}
+     }
+   rootdir_done:
+ 
+diff -uNr x-load-f243938.orig/.gitignore x-load-f243938/.gitignore
+--- x-load-f243938.orig/.gitignore	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/.gitignore	2012-06-07 14:45:39.437648667 -0300
+@@ -0,0 +1,50 @@
++#
++# NOTE! Don't add files that are generated in specific
++# subdirectories here. Add them in the ".gitignore" file
++# in that subdirectory instead.
++#
++# Normal rules
++#
++.*
++*.o
++*.o.*
++*.a
++*.s
++*.ko
++*.so
++*.so.dbg
++*.mod.c
++*.i
++*.lst
++*.symtypes
++
++#
++# Top-level generic files
++#
++x-load
++x-load.*
++System.map
++include/asm/arch
++include/asm/proc
++include/config.h
++include/config.mk
++!.gitignore
++signGP
++MLO
++
++#
++# Generated include files
++#
++
++# stgit generated dirs
++patches-*
++
++# quilt's files
++patches
++series
++
++# cscope files
++cscope.*
++
++*.orig
++*.rej
+diff -uNr x-load-f243938.orig/include/asm/arch-omap3/mem.h x-load-f243938/include/asm/arch-omap3/mem.h
+--- x-load-f243938.orig/include/asm/arch-omap3/mem.h	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap3/mem.h	2012-06-07 14:45:39.453648667 -0300
+@@ -74,6 +74,7 @@
+ #define SDP_SDRC_MDCFG_0_DDR	(0x02584019|B_ALL)
+ #define SDP_SDRC_MDCFG_0_DDR_MICRON_XM	(0x03588019|B_ALL)
+ #define SDP_SDRC_MDCFG_0_DDR_NUMONYX_XM	(0x04590019|B_ALL)
++#define SDP_SDRC_MDCFG_0_DDR_HYNIX	(0x03588019|B_ALL)
+ #endif
+ 
+ #define SDP_SDRC_MR_0_DDR		0x00000032
+@@ -295,6 +296,46 @@
+ #define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | (NUMONYX_XSR_165 << 0)) | \
+ 				(NUMONYX_TXP_165 << 8) | (NUMONYX_TWTR_165 << 16)
+ 
++/*
++ * Hynix part of Overo (165MHz optimized) 6.06ns
++ *   ACTIMA
++ *     ACTIMA
++ *        TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
++ *        TDPL (Twr) = 15/6       = 2.5 -> 3
++ *        TRRD = 12/6     = 2
++ *        TRCD = 18/6     = 3
++ *        TRP = 18/6      = 3
++ *        TRAS = 42/6     = 7
++ *        TRC = 60/6      = 10
++ *        TRFC = 97.5/6    = 17
++ *     ACTIMB
++ *        TWTR = 1
++ *        TCKE = 1
++ *        TXP = 1+1
++ *        XSR = 140/6 = 24
++ */
++#define HYNIX_TDAL_165   6
++#define HYNIX_TDPL_165   3
++#define HYNIX_TRRD_165   2
++#define HYNIX_TRCD_165   3
++#define HYNIX_TRP_165    3
++#define HYNIX_TRAS_165   7
++#define HYNIX_TRC_165   10
++#define HYNIX_TRFC_165  21
++#define HYNIX_V_ACTIMA_165 ((HYNIX_TRFC_165 << 27) | \
++		(HYNIX_TRC_165 << 22) | (HYNIX_TRAS_165 << 18) | \
++		(HYNIX_TRP_165 << 15) | (HYNIX_TRCD_165 << 12) | \
++		(HYNIX_TRRD_165 << 9) | (HYNIX_TDPL_165 << 6) | \
++		(HYNIX_TDAL_165))
++
++#define HYNIX_TWTR_165   1
++#define HYNIX_TCKE_165   1
++#define HYNIX_TXP_165    2
++#define HYNIX_XSR_165    24
++#define HYNIX_V_ACTIMB_165 ((HYNIX_TCKE_165 << 12) | \
++		(HYNIX_XSR_165 << 0) | (HYNIX_TXP_165 << 8) | \
++		(HYNIX_TWTR_165 << 16))
++
+ /* New and compatability speed defines */
+ #if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II) || defined(PRCM_CONFIG_5B)
+ # define L3_100MHZ   /* Use with <= 100MHz SDRAM */
+diff -uNr x-load-f243938.orig/include/asm/arch-omap3/omap3430.h x-load-f243938/include/asm/arch-omap3/omap3430.h
+--- x-load-f243938.orig/include/asm/arch-omap3/omap3430.h	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap3/omap3430.h	2012-06-07 14:45:39.453648667 -0300
+@@ -138,4 +138,60 @@
+ #define ENHANCED_UI_EE_NAME		"750-2075"
+ #endif
+ 
++/*
++ * 343x real hardware:
++ *  ES1     = rev 0
++ *
++ *  ES2 onwards, the value maps to contents of IDCODE register [31:28].
++ *
++ * Note : CPU_3XX_ES20 is used in cache.S.  Please review before changing.
++ */
++#define CPU_3XX_ES10		0
++#define CPU_3XX_ES20		1
++#define CPU_3XX_ES21		2
++#define CPU_3XX_ES30		3
++#define CPU_3XX_ES31		4
++#define CPU_3XX_ES312		7
++#define CPU_3XX_MAX_REV		8
++
++#define CPU_3XX_ID_SHIFT	28
++
++#define WIDTH_8BIT		0x0000
++#define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
++
++/*
++ * Control idcode register contains hawkeye and revision info
++ */
++#define CONTROL_IDCODE		0x4830A204
++#define CONTROL_OMAP_STATUS     0x4800244C
++
++/*
++ * Hawkeye values
++ */
++#define HAWKEYE_OMAP34XX	0xb7ae
++#define HAWKEYE_AM35XX		0xb868
++#define HAWKEYE_OMAP36XX	0xb891
++
++#define HAWKEYE_SHIFT		12
++
++/*
++ * Define CPU families
++ */
++#define CPU_OMAP34XX		0x3400	/* OMAP34xx/OMAP35 devices */
++#define CPU_AM35XX		0x3500	/* AM35xx devices          */
++#define CPU_OMAP36XX		0x3600	/* OMAP36xx devices        */
++
++/*
++ * Control status register values corresponding to cpu variants
++ */
++#define OMAP3503		0x5c00
++#define OMAP3515		0x1c00
++#define OMAP3525		0x4c00
++#define OMAP3530		0x0c00
++
++#define AM3505			0x5c00
++#define AM3517			0x1c00
++
++#define OMAP3730		0x0c00
++
+ #endif  /* _OMAP3430_SYS_H_ */
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/bits.h x-load-f243938/include/asm/arch-omap4/bits.h
+--- x-load-f243938.orig/include/asm/arch-omap4/bits.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/bits.h	2012-06-07 14:45:39.453648667 -0300
+@@ -0,0 +1,48 @@
++/* bits.h
++ * Copyright (c) 2004-2009 Texas Instruments
++ *
++ * This package is free software;  you can redistribute it and/or
++ * modify it under the terms of the license found in the file
++ * named COPYING that should have accompanied this file.
++ *
++ * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
++ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
++ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
++ */
++#ifndef __bits_h
++#define __bits_h 1
++
++#define BIT0  (1<<0)
++#define BIT1  (1<<1)
++#define BIT2  (1<<2)
++#define BIT3  (1<<3)
++#define BIT4  (1<<4)
++#define BIT5  (1<<5)
++#define BIT6  (1<<6)
++#define BIT7  (1<<7)
++#define BIT8  (1<<8)
++#define BIT9  (1<<9)
++#define BIT10 (1<<10)
++#define BIT11 (1<<11)
++#define BIT12 (1<<12)
++#define BIT13 (1<<13)
++#define BIT14 (1<<14)
++#define BIT15 (1<<15)
++#define BIT16 (1<<16)
++#define BIT17 (1<<17)
++#define BIT18 (1<<18)
++#define BIT19 (1<<19)
++#define BIT20 (1<<20)
++#define BIT21 (1<<21)
++#define BIT22 (1<<22)
++#define BIT23 (1<<23)
++#define BIT24 (1<<24)
++#define BIT25 (1<<25)
++#define BIT26 (1<<26)
++#define BIT27 (1<<27)
++#define BIT28 (1<<28)
++#define BIT29 (1<<29)
++#define BIT30 (1<<30)
++#define BIT31 (1<<31)
++
++#endif
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/clocks443x.h x-load-f243938/include/asm/arch-omap4/clocks443x.h
+--- x-load-f243938.orig/include/asm/arch-omap4/clocks443x.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/clocks443x.h	2012-06-07 14:45:39.453648667 -0300
+@@ -0,0 +1,154 @@
++/*
++ * (C) Copyright 2006-2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++  */
++#ifndef _OMAP443X_CLOCKS_H_
++#define _OMAP443X_CLOCKS_H_
++
++#define PLL_STOP        1         /* PER & IVA */
++#define PLL_MN_POWER_BYPASS 	4
++#define PLL_LOW_POWER_BYPASS   5  /* MPU, IVA & CORE */
++#define PLL_FAST_RELOCK_BYPASS 6  /* CORE */
++#define PLL_LOCK        7         /* MPU, IVA, CORE & PER */
++
++/* The following configurations are OPP and SysClk value independant
++ * and hence are defined here. All the other DPLL related values are
++ * tabulated in lowlevel_init.S.
++ */
++
++/* CORE DPLL */
++#  define CORE_M3X2      2        /* 332MHz : CM_CLKSEL1_EMU */
++#  define CORE_SSI_DIV   3        /* 221MHz : CM_CLKSEL_CORE */
++#  define CORE_FUSB_DIV  2        /* 41.5MHz: */
++#  define CORE_L4_DIV    2        /*  83MHz : L4 */
++#  define CORE_L3_DIV    2        /* 166MHz : L3 {DDR} */
++#  define GFX_DIV        2        /*  83MHz : CM_CLKSEL_GFX */
++#  define WKUP_RSM       2        /* 41.5MHz: CM_CLKSEL_WKUP */
++
++/* PER DPLL */
++# define PER_M6X2       3         /* 288MHz: CM_CLKSEL1_EMU */
++# define PER_M5X2       4         /* 216MHz: CM_CLKSEL_CAM */
++# define PER_M4X2       9         /* 96MHz : CM_CLKSEL_DSS-dss1 */
++# define PER_M3X2       16        /* 54MHz : CM_CLKSEL_DSS-tv */
++
++#  define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0a50))
++
++#ifdef PRCM_CLK_CFG2_332MHZ
++# define M_12		0xA6
++# define N_12		0x05
++# define FSEL_12	0x07
++# define M2_12		0x01 /* M3 of 2 */
++
++# define M_12_ES1	0x0E
++# define FSL_12_ES1 0x03
++# define M2_12_ES1  0x1 /* M3 of 2 */
++
++# define M_13       0x14C
++# define N_13       0x0C
++# define FSEL_13	0x03
++# define M2_13		0x01 /* M3 of 2 */
++
++# define M_13_ES1	0x1B2
++# define N_13_ES1	0x10
++# define FSL_13_ES1 0x03
++# define M2_13_ES1	0x01 /* M3 of 2 */
++
++# define M_19p2     0x19F
++# define N_19p2     0x17
++# define FSEL_19p2  0x03
++# define M2_19p2    0x01 /* M3 of 2 */
++
++# define M_19p2_ES1	0x19F
++# define N_19p2_ES1	0x17
++# define FSL_19p2_ES1 0x03
++# define M2_19p2_ES1 0x01 /* M3 of 2 */
++
++# define M_26       0xA6
++# define N_26       0x0C
++# define FSEL_26    0x07
++# define M2_26      0x01 /* M3 of 2 */
++
++# define M_26_ES1	0x1B2
++# define N_26_ES1	0x21
++# define FSL_26_ES1	0x03
++# define M2_26_ES1	0x01 /* M3 of 2 */
++
++# define M_38p4     0x19F
++# define N_38p4     0x2F
++# define FSEL_38p4  0x03
++# define M2_38p4    0x01 /* M3 of 2 */
++
++# define M_38p4_ES1	0x19F
++# define N_38p4_ES1	0x2F
++# define FSL_38p4_ES1 0x03
++# define M2_38p4_ES1 0x01 /* M3 of 2 */
++
++#elif defined(PRCM_CLK_CFG2_266MHZ)
++# define M_12		0x85
++# define N_12       0x05
++# define FSEL_12    0x07
++# define M2_12      0x02 /* M3 of 2 */
++
++# define M_12_ES1	0x85  /* 0x10A */
++# define N_12_ES1	0x05  /* 0x05 */
++# define FSL_12_ES1 0x07  /* 0x7 */
++# define M2_12_ES1  0x2   /* 0x2 with an M3 of 4*/
++
++# define M_13       0x10A
++# define N_13       0x0C
++# define FSEL_13    0x3
++# define M2_13      0x1 /* M3 of 2 */
++
++# define M_13_ES1	0x10A /* 0x214 */
++# define N_13_ES1	0x0C  /* 0xC */
++# define FSL_13_ES1 0x3   /* 0x3 */
++# define M2_13_ES1	0x1   /* 0x2 with an M3 of 4*/
++
++# define M_19p2     0x115
++# define N_19p2     0x13
++# define FSEL_19p2  0x03
++# define M2_19p2    0x01 /* M3 of 2 */
++
++# define M_19p2_ES1	0x115  /* 0x299 */
++# define N_19p2_ES1	0x13   /* 0x17 */
++# define FSL_19p2_ES1 0x03 /* 0x03 */
++# define M2_19p2_ES1 0x01  /* 0x2 with M3 of 4 */
++
++# define M_26		0x85
++# define N_26		0x0C
++# define FSEL_26	0x07
++# define M2_26		0x01 /* M3 of 2 */
++
++# define M_26_ES1	0x85  /* 0x10A */
++# define N_26_ES1	0x0C  /* 0xC */
++# define FSL_26_ES1 0x07  /* 0x7 */
++# define M2_26_ES1	0x01  /* 0x2 with an M3 of 4 */
++
++# define M_38p4     0x11C
++# define N_38p4     0x28
++# define FSEL_38p4  0x03
++# define M2_38p4    0x01 /* M3 of 2 */
++
++# define M_38p4_ES1	0x11C  /* 0x299 */
++# define N_38p4_ES1	0x28   /* 0x2f */
++# define FSL_38p4_ES1 0x03 /* 0x3 */
++# define M2_38p4_ES1 0x01  /* 0x2 with an M3 of 4*/
++
++#endif
++
++#endif  /* endif _OMAP443X_CLOCKS_H_ */
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/clocks.h x-load-f243938/include/asm/arch-omap4/clocks.h
+--- x-load-f243938.orig/include/asm/arch-omap4/clocks.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/clocks.h	2012-06-07 14:45:39.453648667 -0300
+@@ -0,0 +1,36 @@
++/*
++ * (C) Copyright 2006-2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++  */
++#ifndef _OMAP44XX_CLOCKS_H_
++#define _OMAP44XX_CLOCKS_H_
++
++#define LDELAY      12000000
++
++#define S12M		12000000
++#define S13M		13000000
++#define S16_8M		16800000
++#define S19_2M		19200000
++#define S24M		24000000
++#define S26M		26000000
++#define	S27M		27000000
++#define S38_4M		38400000
++
++#include <asm/arch/clocks443x.h>
++
++#endif
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/cpu.h x-load-f243938/include/asm/arch-omap4/cpu.h
+--- x-load-f243938.orig/include/asm/arch-omap4/cpu.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/cpu.h	2012-06-07 14:45:39.453648667 -0300
+@@ -0,0 +1,464 @@
++/*
++ * (C) Copyright 2006-2009
++ * Texas Instruments, <www.ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++#ifndef _OMAP44XX_CPU_H
++#define  _OMAP44XX_CPU_H
++#include <asm/arch/omap4430.h>
++
++/* Register offsets of common modules */
++/* Control */
++#define CONTROL_STATUS			(OMAP44XX_CTRL_BASE + 0x2F0)
++#define OMAP44XX_MCR			(OMAP44XX_CTRL_BASE + 0x8C)
++#define CONTROL_SCALABLE_OMAP_STATUS	(OMAP44XX_CTRL_BASE + 0x44C)
++#define CONTROL_SCALABLE_OMAP_OCP	(OMAP44XX_CTRL_BASE + 0x534)
++
++
++/* Tap Information */
++#define TAP_IDCODE_REG		(OMAP44XX_TAP_BASE+0x204)
++#define PRODUCTION_ID		(OMAP44XX_TAP_BASE+0x208)
++
++/* device type */
++#define DEVICE_MASK		(BIT8|BIT9|BIT10)
++#define TST_DEVICE		0x0
++#define EMU_DEVICE		0x1
++#define HS_DEVICE		0x2
++#define GP_DEVICE		0x3
++
++/* GPMC CS3/cs4/cs6 not avaliable */
++#define GPMC_BASE		(OMAP44XX_GPMC_BASE)
++#define GPMC_SYSCONFIG		(OMAP44XX_GPMC_BASE+0x10)
++#define GPMC_IRQSTATUS		(OMAP44XX_GPMC_BASE+0x18)
++#define GPMC_IRQENABLE		(OMAP44XX_GPMC_BASE+0x1C)
++#define GPMC_TIMEOUT_CONTROL	(OMAP44XX_GPMC_BASE+0x40)
++#define GPMC_CONFIG		(OMAP44XX_GPMC_BASE+0x50)
++#define GPMC_STATUS		(OMAP44XX_GPMC_BASE+0x54)
++
++#define GPMC_CONFIG_CS0		(OMAP44XX_GPMC_BASE+0x60)
++#define GPMC_CONFIG_WIDTH	(0x30)
++
++#define GPMC_CONFIG1		(0x00)
++#define GPMC_CONFIG2		(0x04)
++#define GPMC_CONFIG3		(0x08)
++#define GPMC_CONFIG4		(0x0C)
++#define GPMC_CONFIG5		(0x10)
++#define GPMC_CONFIG6		(0x14)
++#define GPMC_CONFIG7		(0x18)
++#define GPMC_NAND_CMD		(0x1C)
++#define GPMC_NAND_ADR		(0x20)
++#define GPMC_NAND_DAT		(0x24)
++
++#define GPMC_ECC_CONFIG		(0x1F4)
++#define GPMC_ECC_CONTROL	(0x1F8)
++#define GPMC_ECC_SIZE_CONFIG	(0x1FC)
++#define GPMC_ECC1_RESULT	(0x200)
++#define GPMC_ECC2_RESULT	(0x204)
++#define GPMC_ECC3_RESULT	(0x208)
++#define GPMC_ECC4_RESULT	(0x20C)
++#define GPMC_ECC5_RESULT	(0x210)
++#define GPMC_ECC6_RESULT	(0x214)
++#define GPMC_ECC7_RESULT	(0x218)
++#define GPMC_ECC8_RESULT	(0x21C)
++#define GPMC_ECC9_RESULT	(0x220)
++
++#define GPMC_PREFETCH_CONFIG1	(0x1e0)
++#define GPMC_PREFETCH_CONFIG2	(0x1e4)
++#define GPMC_PREFETCH_CONTROL	(0x1ec)
++#define GPMC_PREFETCH_STATUS	(0x1f0)
++
++/* GPMC Mapping */
++# define FLASH_BASE		0x10000000  /* NOR flash (aligned to 256 Meg) */
++# define FLASH_BASE_SDPV1	0x04000000  /* NOR flash (aligned to 64 Meg) */
++# define FLASH_BASE_SDPV2	0x10000000  /* NOR flash (aligned to 256 Meg) */
++# define DEBUG_BASE		0x08000000  /* debug board */
++# define NAND_BASE	0x30000000  /* NAND addr (actual size small port)*/
++# define PISMO2_BASE	0x18000000  /* PISMO2 CS1/2 */
++# define ONENAND_MAP	0x20000000  /* OneNand addr (actual size small port */
++
++/* DMM */
++#define DMM_SYSCONFIG		(OMAP44XX_DMM_BASE+0x10)
++#define DMM_LISA_MAP		(OMAP44XX_DMM_BASE+0x100)
++
++/* SMS */
++#define SMS_SYSCONFIG           (OMAP44XX_SMS_BASE+0x10)
++#define SMS_RG_ATT0             (OMAP44XX_SMS_BASE+0x48)
++#define SMS_CLASS_ARB0          (OMAP44XX_SMS_BASE+0xD0)
++#define BURSTCOMPLETE_GROUP7    BIT31
++
++#define SDRC_CS_CFG		(OMAP44XX_SDRC_BASE+0x40)
++#define OMAP44XX_SDRC_CS0	0x80000000
++#define SDRC_POWER		(OMAP44XX_SDRC_BASE+0x70)
++#define SDRC_MCFG_0		(OMAP44XX_SDRC_BASE+0x80)
++#define SDRC_MR_0		(OMAP44XX_SDRC_BASE+0x84)
++
++/* timer regs offsets (32 bit regs) */
++#define TIDR			0x0      /* r */
++#define TIOCP_CFG		0x10     /* rw */
++#define TISTAT			0x14     /* r */
++#define TISR			0x18     /* rw */
++#define TIER			0x1C     /* rw */
++#define TWER			0x20     /* rw */
++#define TCLR			0x24     /* rw */
++#define TCRR			0x28     /* rw */
++#define TLDR			0x2C     /* rw */
++#define TTGR			0x30     /* rw */
++#define TWPS			0x34     /* r */
++#define TMAR			0x38     /* rw */
++#define TCAR1			0x3c     /* r */
++#define TSICR			0x40     /* rw */
++#define TCAR2			0x44     /* r */
++#define GPT_EN		((0<<2)|BIT1|BIT0) /* enable sys_clk NO-prescale /1 */
++
++/* Watchdog */
++#define WWPS			0x34     /* r */
++#define WSPR			0x48     /* rw */
++#define WD_UNLOCK1		0xAAAA
++#define WD_UNLOCK2		0x5555
++
++/* FIXME */
++#define PRM_RSTCTRL          			0x48307250
++  /* PRCM */
++#define CM_SYS_CLKSEL				0x4a306110
++
++/* PRM.CKGEN module registers */
++#define CM_ABE_PLL_REF_CLKSEL		0x4a30610c
++
++
++/* PRM.WKUP_CM module registers */
++#define CM_WKUP_CLKSTCTRL		0x4a307800
++#define CM_WKUP_L4WKUP_CLKCTRL		0x4a307820
++#define CM_WKUP_WDT1_CLKCTRL		0x4a307828
++#define CM_WKUP_WDT2_CLKCTRL		0x4a307830
++#define CM_WKUP_GPIO1_CLKCTRL		0x4a307838
++#define CM_WKUP_TIMER1_CLKCTRL		0x4a307840
++#define CM_WKUP_TIMER12_CLKCTRL		0x4a307848
++#define CM_WKUP_SYNCTIMER_CLKCTRL	0x4a307850
++#define CM_WKUP_USIM_CLKCTRL		0x4a307858
++#define CM_WKUP_SARRAM_CLKCTRL		0x4a307860
++#define CM_WKUP_KEYBOARD_CLKCTRL	0x4a307878
++#define CM_WKUP_RTC_CLKCTRL		0x4a307880
++#define CM_WKUP_BANDGAP_CLKCTRL		0x4a307888
++
++/* CM1.CKGEN module registers */
++#define CM_CLKSEL_CORE				0x4a004100
++#define CM_CLKSEL_ABE				0x4a004108
++#define CM_DLL_CTRL				0x4a004110
++#define CM_CLKMODE_DPLL_CORE			0x4a004120
++#define CM_IDLEST_DPLL_CORE			0x4a004124
++#define CM_AUTOIDLE_DPLL_CORE			0x4a004128
++#define CM_CLKSEL_DPLL_CORE			0x4a00412c
++#define CM_DIV_M2_DPLL_CORE			0x4a004130
++#define CM_DIV_M3_DPLL_CORE			0x4a004134
++#define CM_DIV_M4_DPLL_CORE			0x4a004138
++#define CM_DIV_M5_DPLL_CORE			0x4a00413c
++#define CM_DIV_M6_DPLL_CORE			0x4a004140
++#define CM_DIV_M7_DPLL_CORE			0x4a004144
++#define CM_SSC_DELTAMSTEP_DPLL_CORE		0x4a004148
++#define CM_SSC_MODFREQDIV_DPLL_CORE		0x4a00414c
++#define CM_EMU_OVERRIDE_DPLL_CORE		0x4a004150
++#define CM_CLKMODE_DPLL_MPU			0x4a004160
++#define CM_IDLEST_DPLL_MPU			0x4a004164
++#define CM_AUTOIDLE_DPLL_MPU			0x4a004168
++#define CM_CLKSEL_DPLL_MPU			0x4a00416c
++#define CM_DIV_M2_DPLL_MPU			0x4a004170
++#define CM_SSC_DELTAMSTEP_DPLL_MPU		0x4a004188
++#define CM_SSC_MODFREQDIV_DPLL_MPU		0x4a00418c
++#define CM_BYPCLK_DPLL_MPU			0x4a00419c
++#define CM_CLKMODE_DPLL_IVA			0x4a0041a0
++#define CM_IDLEST_DPLL_IVA			0x4a0041a4
++#define CM_AUTOIDLE_DPLL_IVA			0x4a0041a8
++#define CM_CLKSEL_DPLL_IVA			0x4a0041ac
++#define CM_DIV_M4_DPLL_IVA			0x4a0041b8
++#define CM_DIV_M5_DPLL_IVA			0x4a0041bc
++#define CM_SSC_DELTAMSTEP_DPLL_IVA		0x4a0041c8
++#define CM_SSC_MODFREQDIV_DPLL_IVA		0x4a0041cc
++#define CM_BYPCLK_DPLL_IVA			0x4a0041dc
++#define CM_CLKMODE_DPLL_ABE			0x4a0041e0
++#define CM_IDLEST_DPLL_ABE			0x4a0041e4
++#define CM_AUTOIDLE_DPLL_ABE			0x4a0041e8
++#define CM_CLKSEL_DPLL_ABE			0x4a0041ec
++#define CM_DIV_M2_DPLL_ABE			0x4a0041f0
++#define CM_DIV_M3_DPLL_ABE			0x4a0041f4
++#define CM_SSC_DELTAMSTEP_DPLL_ABE		0x4a004208
++#define CM_SSC_MODFREQDIV_DPLL_ABE		0x4a00420c
++#define CM_CLKMODE_DPLL_DDRPHY			0x4a004220
++#define CM_IDLEST_DPLL_DDRPHY			0x4a004224
++#define CM_AUTOIDLE_DPLL_DDRPHY			0x4a004228
++#define CM_CLKSEL_DPLL_DDRPHY			0x4a00422c
++#define CM_DIV_M2_DPLL_DDRPHY			0x4a004230
++#define CM_DIV_M4_DPLL_DDRPHY			0x4a004238
++#define CM_DIV_M5_DPLL_DDRPHY			0x4a00423c
++#define CM_DIV_M6_DPLL_DDRPHY			0x4a004240
++#define CM_SSC_DELTAMSTEP_DPLL_DDRPHY		0x4a004248
++
++/* CM1.ABE register offsets */
++#define CM1_ABE_CLKSTCTRL		0x4a004500
++#define CM1_ABE_L4ABE_CLKCTRL		0x4a004520
++#define CM1_ABE_AESS_CLKCTRL		0x4a004528
++#define CM1_ABE_PDM_CLKCTRL		0x4a004530
++#define CM1_ABE_DMIC_CLKCTRL		0x4a004538
++#define CM1_ABE_MCASP_CLKCTRL		0x4a004540
++#define CM1_ABE_MCBSP1_CLKCTRL		0x4a004548
++#define CM1_ABE_MCBSP2_CLKCTRL		0x4a004550
++#define CM1_ABE_MCBSP3_CLKCTRL		0x4a004558
++#define CM1_ABE_SLIMBUS_CLKCTRL		0x4a004560
++#define CM1_ABE_TIMER5_CLKCTRL		0x4a004568
++#define CM1_ABE_TIMER6_CLKCTRL		0x4a004570
++#define CM1_ABE_TIMER7_CLKCTRL		0x4a004578
++#define CM1_ABE_TIMER8_CLKCTRL		0x4a004580
++#define CM1_ABE_WDT3_CLKCTRL		0x4a004588
++
++/* CM1.DSP register offsets */
++#define DSP_CLKSTCTRL			0x4a004400
++#define	DSP_DSP_CLKCTRL			0x4a004420
++
++/* CM2.CKGEN module registers */
++#define CM_CLKSEL_DUCATI_ISS_ROOT		0x4a008100
++#define CM_CLKSEL_USB_60MHz			0x4a008104
++#define CM_SCALE_FCLK				0x4a008108
++#define CM_CORE_DVFS_PERF1			0x4a008110
++#define CM_CORE_DVFS_PERF2			0x4a008114
++#define CM_CORE_DVFS_PERF3			0x4a008118
++#define CM_CORE_DVFS_PERF4			0x4a00811c
++#define CM_CORE_DVFS_CURRENT			0x4a008124
++#define CM_IVA_DVFS_PERF_TESLA			0x4a008128
++#define CM_IVA_DVFS_PERF_IVAHD			0x4a00812c
++#define CM_IVA_DVFS_PERF_ABE			0x4a008130
++#define CM_IVA_DVFS_CURRENT			0x4a008138
++#define CM_CLKMODE_DPLL_PER			0x4a008140
++#define CM_IDLEST_DPLL_PER			0x4a008144
++#define CM_AUTOIDLE_DPLL_PER			0x4a008148
++#define CM_CLKSEL_DPLL_PER			0x4a00814c
++#define CM_DIV_M2_DPLL_PER			0x4a008150
++#define CM_DIV_M3_DPLL_PER			0x4a008154
++#define CM_DIV_M4_DPLL_PER			0x4a008158
++#define CM_DIV_M5_DPLL_PER			0x4a00815c
++#define CM_DIV_M6_DPLL_PER			0x4a008160
++#define CM_DIV_M7_DPLL_PER			0x4a008164
++#define CM_SSC_DELTAMSTEP_DPLL_PER		0x4a008168
++#define CM_SSC_MODFREQDIV_DPLL_PER		0x4a00816c
++#define CM_EMU_OVERRIDE_DPLL_PER		0x4a008170
++#define CM_CLKMODE_DPLL_USB			0x4a008180
++#define CM_IDLEST_DPLL_USB			0x4a008184
++#define CM_AUTOIDLE_DPLL_USB			0x4a008188
++#define CM_CLKSEL_DPLL_USB			0x4a00818c
++#define CM_DIV_M2_DPLL_USB			0x4a008190
++#define CM_SSC_DELTAMSTEP_DPLL_USB		0x4a0081a8
++#define CM_SSC_MODFREQDIV_DPLL_USB		0x4a0081ac
++#define CM_CLKDCOLDO_DPLL_USB			0x4a0081b4
++#define CM_CLKMODE_DPLL_UNIPRO			0x4a0081c0
++#define CM_IDLEST_DPLL_UNIPRO			0x4a0081c4
++#define CM_AUTOIDLE_DPLL_UNIPRO			0x4a0081c8
++#define CM_CLKSEL_DPLL_UNIPRO			0x4a0081cc
++#define CM_DIV_M2_DPLL_UNIPRO			0x4a0081d0
++#define CM_SSC_DELTAMSTEP_DPLL_UNIPRO		0x4a0081e8
++#define CM_SSC_MODFREQDIV_DPLL_UNIPRO		0x4a0081ec
++
++/* CM2.CORE module registers */
++#define CM_L3_1_CLKSTCTRL		0x4a008700
++#define CM_L3_1_DYNAMICDEP		0x4a008708
++#define CM_L3_1_L3_1_CLKCTRL		0x4a008720
++#define CM_L3_2_CLKSTCTRL		0x4a008800
++#define CM_L3_2_DYNAMICDEP		0x4a008808
++#define CM_L3_2_L3_2_CLKCTRL		0x4a008820
++#define CM_L3_2_GPMC_CLKCTRL		0x4a008828
++#define CM_L3_2_OCMC_RAM_CLKCTRL	0x4a008830
++#define CM_DUCATI_CLKSTCTRL		0x4a008900
++#define CM_DUCATI_STATICDEP		0x4a008904
++#define CM_DUCATI_DYNAMICDEP		0x4a008908
++#define CM_DUCATI_DUCATI_CLKCTRL	0x4a008920
++#define CM_SDMA_CLKSTCTRL		0x4a008a00
++#define CM_SDMA_STATICDEP		0x4a008a04
++#define CM_SDMA_DYNAMICDEP		0x4a008a08
++#define CM_SDMA_SDMA_CLKCTRL		0x4a008a20
++#define CM_MEMIF_CLKSTCTRL		0x4a008b00
++#define CM_MEMIF_DMM_CLKCTRL		0x4a008b20
++#define CM_MEMIF_EMIF_FW_CLKCTRL	0x4a008b28
++#define CM_MEMIF_EMIF_1_CLKCTRL		0x4a008b30
++#define CM_MEMIF_EMIF_2_CLKCTRL		0x4a008b38
++#define CM_MEMIF_DLL_CLKCTRL		0x4a008b40
++#define CM_MEMIF_EMIF_H1_CLKCTRL	0x4a008b50
++#define CM_MEMIF_EMIF_H2_CLKCTRL	0x4a008b58
++#define CM_MEMIF_DLL_H_CLKCTRL		0x4a008b60
++#define CM_D2D_CLKSTCTRL		0x4a008c00
++#define CM_D2D_STATICDEP		0x4a008c04
++#define CM_D2D_DYNAMICDEP		0x4a008c08
++#define CM_D2D_SAD2D_CLKCTRL		0x4a008c20
++#define CM_D2D_MODEM_ICR_CLKCTRL	0x4a008c28
++#define CM_D2D_SAD2D_FW_CLKCTRL		0x4a008c30
++#define CM_L4CFG_CLKSTCTRL		0x4a008d00
++#define CM_L4CFG_DYNAMICDEP		0x4a008d08
++#define CM_L4CFG_L4_CFG_CLKCTRL		0x4a008d20
++#define CM_L4CFG_HW_SEM_CLKCTRL		0x4a008d28
++#define CM_L4CFG_MAILBOX_CLKCTRL	0x4a008d30
++#define CM_L4CFG_SAR_ROM_CLKCTRL	0x4a008d38
++#define CM_L3INSTR_CLKSTCTRL		0x4a008e00
++#define CM_L3INSTR_L3_3_CLKCTRL		0x4a008e20
++#define CM_L3INSTR_L3_INSTR_CLKCTRL	0x4a008e28
++#define CM_L3INSTR_OCP_WP1_CLKCTRL	0x4a008e40
++
++/* CM2.L4PER register offsets */
++#define CM_L4PER_CLKSTCTRL		0x4a009400
++#define CM_L4PER_DYNAMICDEP		0x4a009408
++#define CM_L4PER_ADC_CLKCTRL		0x4a009420
++#define CM_L4PER_DMTIMER10_CLKCTRL	0x4a009428
++#define CM_L4PER_DMTIMER11_CLKCTRL	0x4a009430
++#define CM_L4PER_DMTIMER2_CLKCTRL	0x4a009438
++#define CM_L4PER_DMTIMER3_CLKCTRL	0x4a009440
++#define CM_L4PER_DMTIMER4_CLKCTRL	0x4a009448
++#define CM_L4PER_DMTIMER9_CLKCTRL	0x4a009450
++#define CM_L4PER_ELM_CLKCTRL		0x4a009458
++#define CM_L4PER_GPIO2_CLKCTRL		0x4a009460
++#define CM_L4PER_GPIO3_CLKCTRL		0x4a009468
++#define CM_L4PER_GPIO4_CLKCTRL		0x4a009470
++#define CM_L4PER_GPIO5_CLKCTRL		0x4a009478
++#define CM_L4PER_GPIO6_CLKCTRL		0x4a009480
++#define CM_L4PER_HDQ1W_CLKCTRL		0x4a009488
++#define CM_L4PER_HECC1_CLKCTRL		0x4a009490
++#define CM_L4PER_HECC2_CLKCTRL		0x4a009498
++#define CM_L4PER_I2C1_CLKCTRL		0x4a0094a0
++#define CM_L4PER_I2C2_CLKCTRL		0x4a0094a8
++#define CM_L4PER_I2C3_CLKCTRL		0x4a0094b0
++#define CM_L4PER_I2C4_CLKCTRL		0x4a0094b8
++#define CM_L4PER_L4PER_CLKCTRL		0x4a0094c0
++#define CM_L4PER_MCASP2_CLKCTRL		0x4a0094d0
++#define CM_L4PER_MCASP3_CLKCTRL		0x4a0094d8
++#define CM_L4PER_MCBSP4_CLKCTRL		0x4a0094e0
++#define CM_L4PER_MGATE_CLKCTRL		0x4a0094e8
++#define CM_L4PER_MCSPI1_CLKCTRL		0x4a0094f0
++#define CM_L4PER_MCSPI2_CLKCTRL		0x4a0094f8
++#define CM_L4PER_MCSPI3_CLKCTRL		0x4a009500
++#define CM_L4PER_MCSPI4_CLKCTRL		0x4a009508
++#define CM_L4PER_MMCSD3_CLKCTRL		0x4a009520
++#define CM_L4PER_MMCSD4_CLKCTRL		0x4a009528
++#define CM_L4PER_MSPROHG_CLKCTRL	0x4a009530
++#define CM_L4PER_SLIMBUS2_CLKCTRL	0x4a009538
++#define CM_L4PER_UART1_CLKCTRL		0x4a009540
++#define CM_L4PER_UART2_CLKCTRL		0x4a009548
++#define CM_L4PER_UART3_CLKCTRL		0x4a009550
++#define CM_L4PER_UART4_CLKCTRL		0x4a009558
++#define CM_L4PER_MMCSD5_CLKCTRL		0x4a009560
++#define CM_L4PER_I2C5_CLKCTRL		0x4a009568
++#define CM_L4SEC_CLKSTCTRL		0x4a009580
++#define CM_L4SEC_STATICDEP		0x4a009584
++#define CM_L4SEC_DYNAMICDEP		0x4a009588
++#define CM_L4SEC_AES1_CLKCTRL		0x4a0095a0
++#define CM_L4SEC_AES2_CLKCTRL		0x4a0095a8
++#define CM_L4SEC_DES3DES_CLKCTRL	0x4a0095b0
++#define CM_L4SEC_PKAEIP29_CLKCTRL	0x4a0095b8
++#define CM_L4SEC_RNG_CLKCTRL		0x4a0095c0
++#define CM_L4SEC_SHA2MD51_CLKCTRL	0x4a0095c8
++#define CM_L4SEC_CRYPTODMA_CLKCTRL	0x4a0095d8
++
++/* CM2.IVAHD */
++#define IVAHD_CLKSTCTRL			0x4a008f00
++#define IVAHD_IVAHD_CLKCTRL		0x4a008f20
++#define IVAHD_SL2_CLKCTRL		0x4a008f28
++
++/* CM2.L3INIT */
++#define CM_L3INIT_HSMMC1_CLKCTRL	0x4a009328
++#define CM_L3INIT_HSMMC2_CLKCTRL	0x4a009330
++#define CM_L3INIT_HSI_CLKCTRL           0x4a009338
++#define CM_L3INIT_UNIPRO1_CLKCTRL       0x4a009340
++#define CM_L3INIT_HSUSBHOST_CLKCTRL     0x4a009358
++#define CM_L3INIT_HSUSBOTG_CLKCTRL      0x4a009360
++#define CM_L3INIT_HSUSBTLL_CLKCTRL      0x4a009368
++#define CM_L3INIT_P1500_CLKCTRL         0x4a009378
++#define CM_L3INIT_FSUSB_CLKCTRL         0x4a0093d0
++#define CM_L3INIT_USBPHY_CLKCTRL        0x4a0093e0
++
++/* CM2.CAM */
++#define CM_CAM_CLKSTCTRL                0x4a009000
++#define CM_CAM_ISS_CLKCTRL              0x4a009020
++#define CM_CAM_FDIF_CLKCTRL             0x4a009028
++
++/* CM2.DSS */
++#define CM_DSS_CLKSTCTRL                0x4a009100
++#define CM_DSS_DSS_CLKCTRL              0x4a009120
++#define CM_DSS_DEISS_CLKCTRL            0x4a009128
++
++/* CM2.SGX */
++#define CM_SGX_CLKSTCTRL                0x4a009200
++#define CM_SGX_SGX_CLKCTRL              0x4a009220
++
++/* SMX-APE */
++#define PM_RT_APE_BASE_ADDR_ARM		(SMX_APE_BASE + 0x10000)
++#define PM_GPMC_BASE_ADDR_ARM		(SMX_APE_BASE + 0x12400)
++#define PM_OCM_RAM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12800)
++#define PM_OCM_ROM_BASE_ADDR_ARM	(SMX_APE_BASE + 0x12C00)
++#define PM_IVA2_BASE_ADDR_ARM		(SMX_APE_BASE + 0x14000)
++
++#define RT_REQ_INFO_PERMISSION_1	(PM_RT_APE_BASE_ADDR_ARM + 0x68)
++#define RT_READ_PERMISSION_0		(PM_RT_APE_BASE_ADDR_ARM + 0x50)
++#define RT_WRITE_PERMISSION_0		(PM_RT_APE_BASE_ADDR_ARM + 0x58)
++#define RT_ADDR_MATCH_1			(PM_RT_APE_BASE_ADDR_ARM + 0x60)
++
++#define GPMC_REQ_INFO_PERMISSION_0	(PM_GPMC_BASE_ADDR_ARM + 0x48)
++#define GPMC_READ_PERMISSION_0		(PM_GPMC_BASE_ADDR_ARM + 0x50)
++#define GPMC_WRITE_PERMISSION_0		(PM_GPMC_BASE_ADDR_ARM + 0x58)
++
++#define OCM_REQ_INFO_PERMISSION_0	(PM_OCM_RAM_BASE_ADDR_ARM + 0x48)
++#define OCM_READ_PERMISSION_0		(PM_OCM_RAM_BASE_ADDR_ARM + 0x50)
++#define OCM_WRITE_PERMISSION_0		(PM_OCM_RAM_BASE_ADDR_ARM + 0x58)
++#define OCM_ADDR_MATCH_2		(PM_OCM_RAM_BASE_ADDR_ARM + 0x80)
++
++#define IVA2_REQ_INFO_PERMISSION_0	(PM_IVA2_BASE_ADDR_ARM + 0x48)
++#define IVA2_READ_PERMISSION_0		(PM_IVA2_BASE_ADDR_ARM + 0x50)
++#define IVA2_WRITE_PERMISSION_0		(PM_IVA2_BASE_ADDR_ARM + 0x58)
++
++#define IVA2_REQ_INFO_PERMISSION_1	(PM_IVA2_BASE_ADDR_ARM + 0x68)
++#define IVA2_READ_PERMISSION_1		(PM_IVA2_BASE_ADDR_ARM + 0x70)
++#define IVA2_WRITE_PERMISSION_1		(PM_IVA2_BASE_ADDR_ARM + 0x78)
++
++#define IVA2_REQ_INFO_PERMISSION_2	(PM_IVA2_BASE_ADDR_ARM + 0x88)
++#define IVA2_READ_PERMISSION_2		(PM_IVA2_BASE_ADDR_ARM + 0x90)
++#define IVA2_WRITE_PERMISSION_2		(PM_IVA2_BASE_ADDR_ARM + 0x98)
++
++#define IVA2_REQ_INFO_PERMISSION_3	(PM_IVA2_BASE_ADDR_ARM + 0xA8)
++#define IVA2_READ_PERMISSION_3		(PM_IVA2_BASE_ADDR_ARM + 0xB0)
++#define IVA2_WRITE_PERMISSION_3		(PM_IVA2_BASE_ADDR_ARM + 0xB8)
++
++/* I2C base */
++#define I2C_BASE1		(OMAP44XX_L4_PER + 0x70000)
++#define I2C_BASE2		(OMAP44XX_L4_PER + 0x72000)
++#define I2C_BASE3		(OMAP44XX_L4_PER + 0x60000)
++
++#ifdef CONFIG_LCD
++	extern void lcd_disable(void);
++	extern void lcd_panel_disable(void);
++#endif
++
++/* Silicon revisions */
++#define OMAP4430_SILICON_ID_INVALID	0
++#define OMAP4430_ES1_0	1
++#define OMAP4430_ES2_0	2
++#define OMAP4430_ES2_1	3
++
++#ifndef	__ASSEMBLY__
++/*Functions for silicon revision */
++unsigned int omap_revision(void);
++unsigned int cortex_a9_rev(void);
++
++void big_delay(unsigned int count);
++#endif
++
++#endif
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/mem.h x-load-f243938/include/asm/arch-omap4/mem.h
+--- x-load-f243938.orig/include/asm/arch-omap4/mem.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/mem.h	2012-06-07 14:45:39.453648667 -0300
+@@ -0,0 +1,285 @@
++/*
++ * (C) Copyright 2006-2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef _OMAP44XX_MEM_H_
++#define _OMAP44XX_MEM_H_
++
++#ifndef __ASSEMBLY__
++
++typedef enum {
++	STACKED		= 0,
++	IP_DDR		= 1,
++	COMBO_DDR	= 2,
++	IP_SDR	 	= 3,
++} mem_t;
++
++/* Memory that can be connected to GPMC */
++#define GPMC_NOR            0
++#define GPMC_NAND           1
++#define GPMC_MDOC           2
++#define GPMC_ONENAND        3
++#define MMC_NAND            4
++#define MMC_ONENAND         5
++#define GPMC_NONE           6
++#define GPMC_ONENAND_TRY    7
++
++#endif
++
++
++/* New and compatability speed defines */
++#if defined(PRCM_CLK_CFG2_200MHZ) || defined(PRCM_CONFIG_II)\
++		|| defined(PRCM_CONFIG_5B)
++# define L3_100MHZ   /* Use with <= 100MHz SDRAM */
++#elif defined(PRCM_CLK_CFG2_266MHZ) || defined(PRCM_CONFIG_III)\
++		|| defined(PRCM_CONFIG_5A)
++# define L3_133MHZ    /* Use with <= 133MHz SDRAM*/
++#elif defined(PRCM_CLK_CFG2_332MHZ) || defined(PRCM_CONFIG_I) \
++		|| defined(PRCM_CONFIG_2)
++# define L3_165MHZ    /* Use with <= 165MHz SDRAM (L3=166 on 4430) */
++#endif
++
++/*
++ * GPMC settings -
++ * Definitions is as per the following format
++ * # define <PART>_GPMC_CONFIG<x> <value>
++ * Where:
++ * PART is the part name e.g. STNOR - Intel Strata Flash
++ * x is GPMC config registers from 1 to 6 (there will be 6 macros)
++ * Value is corresponding value
++ *
++ * For every valid PRCM configuration there should be only one definition of
++ * the same. if values are independent of the board, this definition will be
++ * present in this file if values are dependent on the board, then this should
++ * go into corresponding mem-boardName.h file
++ *
++ * Currently valid part Names are (PART):
++ * STNOR - Intel Strata Flash
++ * SMNAND - Samsung NAND
++ * M_NAND - Micron Large page x16 NAND
++ * MPDB - H4 MPDB board
++ * SBNOR - Sibley NOR
++ * ONNAND - Samsung One NAND
++ *
++ * include/configs/file.h contains the defn - for all CS we are interested
++ * #define OMAP44XX_GPMC_CSx PART
++ * #define OMAP44XX_GPMC_CSx_SIZE Size
++ * #define OMAP44XX_GPMC_CSx_MAP Map
++ * Where:
++ * x - CS number
++ * PART - Part Name as defined above
++ * SIZE - how big is the mapping to be
++ *   GPMC_SIZE_128M - 0x8
++ *   GPMC_SIZE_64M  - 0xC
++ *   GPMC_SIZE_32M  - 0xE
++ *   GPMC_SIZE_16M  - 0xF
++ * MAP  - Map this CS to which address(GPMC address space)- Absolute address
++ *   >>24 before being used.
++ */
++#define GPMC_SIZE_128M  0x8
++#define GPMC_SIZE_64M   0xC
++#define GPMC_SIZE_32M   0xE
++#define GPMC_SIZE_16M   0xF
++
++#if defined(L3_100MHZ)
++# define SMNAND_GPMC_CONFIG1 0x0
++# define SMNAND_GPMC_CONFIG2 0x00141400
++# define SMNAND_GPMC_CONFIG3 0x00141400
++# define SMNAND_GPMC_CONFIG4 0x0F010F01
++# define SMNAND_GPMC_CONFIG5 0x010C1414
++# define SMNAND_GPMC_CONFIG6 0x00000A80
++
++# define M_NAND_GPMC_CONFIG1 0x00001800
++# define M_NAND_GPMC_CONFIG2 0x00141400
++# define M_NAND_GPMC_CONFIG3 0x00141400
++# define M_NAND_GPMC_CONFIG4 0x0F010F01
++# define M_NAND_GPMC_CONFIG5 0x010C1414
++# define M_NAND_GPMC_CONFIG6 0x1f0f0A80
++
++# define STNOR_GPMC_CONFIG1  0x3
++# define STNOR_GPMC_CONFIG2  0x000f0f01
++# define STNOR_GPMC_CONFIG3  0x00050502
++# define STNOR_GPMC_CONFIG4  0x0C060C06
++# define STNOR_GPMC_CONFIG5  0x01131F1F
++# define STNOR_GPMC_CONFIG6  0x1F0F0000
++
++# define MPDB_GPMC_CONFIG1   0x00011000
++# define MPDB_GPMC_CONFIG2   0x001F1F00
++# define MPDB_GPMC_CONFIG3   0x00080802
++# define MPDB_GPMC_CONFIG4   0x1C091C09
++# define MPDB_GPMC_CONFIG5   0x031A1F1F
++# define MPDB_GPMC_CONFIG6   0x000003C2
++#endif
++
++#if defined(L3_133MHZ)
++# define SMNAND_GPMC_CONFIG1 0x00000800
++# define SMNAND_GPMC_CONFIG2 0x00141400
++# define SMNAND_GPMC_CONFIG3 0x00141400
++# define SMNAND_GPMC_CONFIG4 0x0F010F01
++# define SMNAND_GPMC_CONFIG5 0x010C1414
++# define SMNAND_GPMC_CONFIG6 0x1F0F0A80
++# define SMNAND_GPMC_CONFIG7 0x00000C44
++
++# define M_NAND_GPMC_CONFIG1 0x00001800 /* might reuse smnand, with |= 1000 */
++# define M_NAND_GPMC_CONFIG2 0x00141400
++# define M_NAND_GPMC_CONFIG3 0x00141400
++# define M_NAND_GPMC_CONFIG4 0x0F010F01
++# define M_NAND_GPMC_CONFIG5 0x010C1414
++# define M_NAND_GPMC_CONFIG6 0x1F0F0A80
++# define M_NAND_GPMC_CONFIG7 0x00000C44
++
++# define STNOR_GPMC_CONFIG1  0x1203
++# define STNOR_GPMC_CONFIG2  0x00151501
++# define STNOR_GPMC_CONFIG3  0x00060602
++# define STNOR_GPMC_CONFIG4  0x10081008
++# define STNOR_GPMC_CONFIG5  0x01131F1F
++# define STNOR_GPMC_CONFIG6  0x1F0F04c4
++
++# define SIBNOR_GPMC_CONFIG1  0x1200
++# define SIBNOR_GPMC_CONFIG2  0x001f1f00
++# define SIBNOR_GPMC_CONFIG3  0x00080802
++# define SIBNOR_GPMC_CONFIG4  0x1C091C09
++# define SIBNOR_GPMC_CONFIG5  0x01131F1F
++# define SIBNOR_GPMC_CONFIG6  0x1F0F03C2
++
++/* ES1 SDP and ES1 chip Debug FPGA */
++# define MPDB_GPMC_CONFIG1  0x00011000
++# define MPDB_GPMC_CONFIG2  0x001f1f01
++# define MPDB_GPMC_CONFIG3  0x00080803
++# define MPDB_GPMC_CONFIG4  0x1C091C09
++# define MPDB_GPMC_CONFIG5  0x041f1F1F
++# define MPDB_GPMC_CONFIG6  0x000004C4
++
++/* ES2 SDP and ES2 chip Debug FPGA */
++# define SDPV2_MPDB_GPMC_CONFIG1  0x00611200
++# define SDPV2_MPDB_GPMC_CONFIG2  0x001F1F01
++# define SDPV2_MPDB_GPMC_CONFIG3  0x00080803
++# define SDPV2_MPDB_GPMC_CONFIG4  0x1D091D09
++# define SDPV2_MPDB_GPMC_CONFIG5  0x041D1F1F
++# define SDPV2_MPDB_GPMC_CONFIG6  0x1D0904C4
++
++# define P2_GPMC_CONFIG1  0x0
++# define P2_GPMC_CONFIG2  0x0
++# define P2_GPMC_CONFIG3  0x0
++# define P2_GPMC_CONFIG4  0x0
++# define P2_GPMC_CONFIG5  0x0
++# define P2_GPMC_CONFIG6  0x0
++
++# define ONENAND_GPMC_CONFIG1 0x00001200
++# define ONENAND_GPMC_CONFIG2 0x000c0c01
++# define ONENAND_GPMC_CONFIG3 0x00030301
++# define ONENAND_GPMC_CONFIG4 0x0c040c04
++# define ONENAND_GPMC_CONFIG5 0x010C1010
++# define ONENAND_GPMC_CONFIG6 0x1F060000
++
++#endif /* endif L3_133MHZ */
++
++#if defined(L3_165MHZ)
++# define SMNAND_GPMC_CONFIG1 0x00000800
++# define SMNAND_GPMC_CONFIG2 0x00060600
++# define SMNAND_GPMC_CONFIG3 0x00060401
++# define SMNAND_GPMC_CONFIG4 0x05010801
++# define SMNAND_GPMC_CONFIG5 0x00090B0B
++# define SMNAND_GPMC_CONFIG6 0x050001C0
++# define SMNAND_GPMC_CONFIG7 0x00000C44
++
++# define M_NAND_GPMC_CONFIG1 0x00001800
++# define M_NAND_GPMC_CONFIG2 0x00141400
++# define M_NAND_GPMC_CONFIG3 0x00141400
++# define M_NAND_GPMC_CONFIG4 0x0F010F01
++# define M_NAND_GPMC_CONFIG5 0x010C1414
++# define M_NAND_GPMC_CONFIG6 0x1F0F0A80
++# define M_NAND_GPMC_CONFIG7 0x00000C44
++
++# define STNOR_GPMC_CONFIG1  0x3
++# define STNOR_GPMC_CONFIG2  0x00151501
++# define STNOR_GPMC_CONFIG3  0x00060602
++# define STNOR_GPMC_CONFIG4  0x11091109
++# define STNOR_GPMC_CONFIG5  0x01141F1F
++# define STNOR_GPMC_CONFIG6  0x1F0F04c4
++
++# define SIBNOR_GPMC_CONFIG1  0x1200
++# define SIBNOR_GPMC_CONFIG2  0x001f1f00
++# define SIBNOR_GPMC_CONFIG3  0x00080802
++# define SIBNOR_GPMC_CONFIG4  0x1C091C09
++# define SIBNOR_GPMC_CONFIG5  0x01131F1F
++# define SIBNOR_GPMC_CONFIG6  0x1F0F03C2
++
++# define SDPV2_MPDB_GPMC_CONFIG1  0x00611200
++# define SDPV2_MPDB_GPMC_CONFIG2  0x001F1F01
++# define SDPV2_MPDB_GPMC_CONFIG3  0x00080803
++# define SDPV2_MPDB_GPMC_CONFIG4  0x1D091D09
++# define SDPV2_MPDB_GPMC_CONFIG5  0x041D1F1F
++# define SDPV2_MPDB_GPMC_CONFIG6  0x1D0904C4
++
++# define MPDB_GPMC_CONFIG1  0x00011000
++# define MPDB_GPMC_CONFIG2  0x001f1f01
++# define MPDB_GPMC_CONFIG3  0x00080803
++# define MPDB_GPMC_CONFIG4  0x1c0b1c0a
++# define MPDB_GPMC_CONFIG5  0x041f1F1F
++# define MPDB_GPMC_CONFIG6  0x1F0F04C4
++
++# define LAB_ENET_GPMC_CONFIG1  0x00611000
++# define LAB_ENET_GPMC_CONFIG2  0x001F1F01
++# define LAB_ENET_GPMC_CONFIG3  0x00080803
++# define LAB_ENET_GPMC_CONFIG4  0x1D091D09
++# define LAB_ENET_GPMC_CONFIG5  0x041D1F1F
++# define LAB_ENET_GPMC_CONFIG6  0x1D0904C4
++
++# define P2_GPMC_CONFIG1  0x0
++# define P2_GPMC_CONFIG2  0x0
++# define P2_GPMC_CONFIG3  0x0
++# define P2_GPMC_CONFIG4  0x0
++# define P2_GPMC_CONFIG5  0x0
++# define P2_GPMC_CONFIG6  0x0
++
++# define ONENAND_GPMC_CONFIG1 0x00001200
++# define ONENAND_GPMC_CONFIG2 0x000F0F01
++# define ONENAND_GPMC_CONFIG3 0x00030301
++# define ONENAND_GPMC_CONFIG4 0x0F040F04
++# define ONENAND_GPMC_CONFIG5 0x010F1010
++# define ONENAND_GPMC_CONFIG6 0x1F060000
++
++#endif
++
++/* max number of GPMC Chip Selects */
++#define GPMC_MAX_CS	8
++/* max number of GPMC regs */
++#define GPMC_MAX_REG	7
++
++#define PISMO1_NOR	1
++#define PISMO1_NAND	2
++#define PISMO2_CS0	3
++#define PISMO2_CS1	4
++#define PISMO1_ONENAND	5
++#define DBG_MPDB	6
++#define PISMO2_NAND_CS0 7
++#define PISMO2_NAND_CS1 8
++
++/* make it readable for the gpmc_init */
++#define PISMO1_NOR_BASE		FLASH_BASE
++#define PISMO1_NAND_BASE	NAND_BASE
++#define PISMO2_CS0_BASE		PISMO2_MAP1
++#define PISMO1_ONEN_BASE	ONENAND_MAP
++#define DBG_MPDB_BASE		DEBUG_BASE
++
++#endif /* endif _OMAP44XX_MEM_H_ */
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/mmc.h x-load-f243938/include/asm/arch-omap4/mmc.h
+--- x-load-f243938.orig/include/asm/arch-omap4/mmc.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/mmc.h	2012-06-07 14:45:39.453648667 -0300
+@@ -0,0 +1,235 @@
++/*
++ * (C) Copyright 2008
++ * Texas Instruments, <www.ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation's version 2 of
++ * the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef MMC_H
++#define MMC_H
++
++#include "mmc_host_def.h"
++
++/* Responses */
++#define RSP_TYPE_NONE	  (RSP_TYPE_NORSP   | CCCE_NOCHECK | CICE_NOCHECK)
++#define RSP_TYPE_R1	  (RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
++#define RSP_TYPE_R1B	  (RSP_TYPE_LGHT48B | CCCE_CHECK   | CICE_CHECK)
++#define RSP_TYPE_R2	  (RSP_TYPE_LGHT136 | CCCE_CHECK   | CICE_NOCHECK)
++#define RSP_TYPE_R3	  (RSP_TYPE_LGHT48  | CCCE_NOCHECK | CICE_NOCHECK)
++#define RSP_TYPE_R4	  (RSP_TYPE_LGHT48  | CCCE_NOCHECK | CICE_NOCHECK)
++#define RSP_TYPE_R5	  (RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
++#define RSP_TYPE_R6	  (RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
++#define RSP_TYPE_R7	  (RSP_TYPE_LGHT48  | CCCE_CHECK   | CICE_CHECK)
++
++/* All supported commands */
++#define MMC_CMD0          (INDEX(0)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD1          (INDEX(1)  | RSP_TYPE_R3   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD2          (INDEX(2)  | RSP_TYPE_R2   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD3          (INDEX(3)  | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_SDCMD3        (INDEX(3)  | RSP_TYPE_R6   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD4          (INDEX(4)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD6          (INDEX(6)  | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD7_SELECT   (INDEX(7)  | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD7_DESELECT (INDEX(7)  | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD8          (INDEX(8)  | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
++#define MMC_SDCMD8        (INDEX(8)  | RSP_TYPE_R7   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD9          (INDEX(9)  | RSP_TYPE_R2   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD12         (INDEX(12) | RSP_TYPE_R1B  | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD13         (INDEX(13) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD15         (INDEX(15) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD16         (INDEX(16) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_CMD17         (INDEX(17) | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
++#define MMC_CMD24         (INDEX(24) | RSP_TYPE_R1   | DP_DATA    | DDIR_WRITE)
++#define MMC_ACMD6         (INDEX(6)  | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_ACMD41        (INDEX(41) | RSP_TYPE_R3   | DP_NO_DATA | DDIR_WRITE)
++#define MMC_ACMD51        (INDEX(51) | RSP_TYPE_R1   | DP_DATA    | DDIR_READ)
++#define MMC_CMD55         (INDEX(55) | RSP_TYPE_R1   | DP_NO_DATA | DDIR_WRITE)
++
++#define MMC_AC_CMD_RCA_MASK     (unsigned int)(0xFFFF << 16)
++#define MMC_BC_CMD_DSR_MASK     (unsigned int)(0xFFFF << 16)
++#define MMC_DSR_DEFAULT         (0x0404)
++#define SD_CMD8_CHECK_PATTERN	(0xAA)
++#define SD_CMD8_2_7_3_6_V_RANGE	(0x01 << 8)
++
++/* Clock Configurations and Macros */
++
++#define MMC_CLOCK_REFERENCE		(96)
++#define MMC_RELATIVE_CARD_ADDRESS	(0x1234)
++#define MMC_INIT_SEQ_CLK		(MMC_CLOCK_REFERENCE * 1000 / 80)
++#define MMC_400kHz_CLK			(MMC_CLOCK_REFERENCE * 1000 / 400)
++#define CLKDR(r, f, u)			((((r)*100) / ((f)*(u))) + 1)
++#define CLKD(f, u)			(CLKDR(MMC_CLOCK_REFERENCE, f, u))
++
++#define MMC_OCR_REG_ACCESS_MODE_MASK			(0x3 << 29)
++#define MMC_OCR_REG_ACCESS_MODE_BYTE    		(0x0 << 29)
++#define MMC_OCR_REG_ACCESS_MODE_SECTOR  		(0x2 << 29)
++
++#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_MASK		(0x1 << 30)
++#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_BYTE		(0x0 << 30)
++#define MMC_OCR_REG_HOST_CAPACITY_SUPPORT_SECTOR	(0x1 << 30)
++
++#define MMC_SD2_CSD_C_SIZE_LSB_MASK         (0xFFFF)
++#define MMC_SD2_CSD_C_SIZE_MSB_MASK         (0x003F)
++#define MMC_SD2_CSD_C_SIZE_MSB_OFFSET       (16)
++#define MMC_CSD_C_SIZE_LSB_MASK             (0x0003)
++#define MMC_CSD_C_SIZE_MSB_MASK             (0x03FF)
++#define MMC_CSD_C_SIZE_MSB_OFFSET           (2)
++
++#define MMC_CSD_TRAN_SPEED_UNIT_MASK        (0x07 << 0)
++#define MMC_CSD_TRAN_SPEED_FACTOR_MASK      (0x0F << 3)
++#define MMC_CSD_TRAN_SPEED_UNIT_100MHZ      (0x3 << 0)
++#define MMC_CSD_TRAN_SPEED_FACTOR_1_0       (0x01 << 3)
++#define MMC_CSD_TRAN_SPEED_FACTOR_8_0       (0x0F << 3)
++
++typedef struct {
++	unsigned not_used:1;
++	unsigned crc:7;
++	unsigned ecc:2;
++	unsigned file_format:2;
++	unsigned tmp_write_protect:1;
++	unsigned perm_write_protect:1;
++	unsigned copy:1;
++	unsigned file_format_grp:1;
++	unsigned content_prot_app:1;
++	unsigned reserved_1:4;
++	unsigned write_bl_partial:1;
++	unsigned write_bl_len:4;
++	unsigned r2w_factor:3;
++	unsigned default_ecc:2;
++	unsigned wp_grp_enable:1;
++	unsigned wp_grp_size:5;
++	unsigned erase_grp_mult:5;
++	unsigned erase_grp_size:5;
++	unsigned c_size_mult:3;
++	unsigned vdd_w_curr_max:3;
++	unsigned vdd_w_curr_min:3;
++	unsigned vdd_r_curr_max:3;
++	unsigned vdd_r_curr_min:3;
++	unsigned c_size_lsb:2;
++	unsigned c_size_msb:10;
++	unsigned reserved_2:2;
++	unsigned dsr_imp:1;
++	unsigned read_blk_misalign:1;
++	unsigned write_blk_misalign:1;
++	unsigned read_bl_partial:1;
++	unsigned read_bl_len:4;
++	unsigned ccc:12;
++	unsigned tran_speed:8;
++	unsigned nsac:8;
++	unsigned taac:8;
++	unsigned reserved_3:2;
++	unsigned spec_vers:4;
++	unsigned csd_structure:2;
++} mmc_csd_reg_t;
++
++/* csd for sd2.0 */
++typedef struct {
++	unsigned not_used:1;
++	unsigned crc:7;
++	unsigned reserved_1:2;
++	unsigned file_format:2;
++	unsigned tmp_write_protect:1;
++	unsigned perm_write_protect:1;
++	unsigned copy:1;
++	unsigned file_format_grp:1;
++	unsigned reserved_2:5;
++	unsigned write_bl_partial:1;
++	unsigned write_bl_len:4;
++	unsigned r2w_factor:3;
++	unsigned reserved_3:2;
++	unsigned wp_grp_enable:1;
++	unsigned wp_grp_size:7;
++	unsigned sector_size:7;
++	unsigned erase_blk_len:1;
++	unsigned reserved_4:1;
++	unsigned c_size_lsb:16;
++	unsigned c_size_msb:6;
++	unsigned reserved_5:6;
++	unsigned dsr_imp:1;
++	unsigned read_blk_misalign:1;
++	unsigned write_blk_misalign:1;
++	unsigned read_bl_partial:1;
++	unsigned read_bl_len:4;
++	unsigned ccc:12;
++	unsigned tran_speed:8;
++	unsigned nsac:8;
++	unsigned taac:8;
++	unsigned reserved_6:6;
++	unsigned csd_structure:2;
++} mmc_sd2_csd_reg_t;
++
++/* extended csd - 512 bytes long */
++typedef struct {
++	unsigned char reserved_1[181];
++	unsigned char erasedmemorycontent;
++	unsigned char reserved_2;
++	unsigned char buswidthmode;
++	unsigned char reserved_3;
++	unsigned char highspeedinterfacetiming;
++	unsigned char reserved_4;
++	unsigned char powerclass;
++	unsigned char reserved_5;
++	unsigned char commandsetrevision;
++	unsigned char reserved_6;
++	unsigned char commandset;
++	unsigned char extendedcsdrevision;
++	unsigned char reserved_7;
++	unsigned char csdstructureversion;
++	unsigned char reserved_8;
++	unsigned char cardtype;
++	unsigned char reserved_9[3];
++	unsigned char powerclass_52mhz_1_95v;
++	unsigned char powerclass_26mhz_1_95v;
++	unsigned char powerclass_52mhz_3_6v;
++	unsigned char powerclass_26mhz_3_6v;
++	unsigned char reserved_10;
++	unsigned char minreadperf_4b_26mhz;
++	unsigned char minwriteperf_4b_26mhz;
++	unsigned char minreadperf_8b_26mhz_4b_52mhz;
++	unsigned char minwriteperf_8b_26mhz_4b_52mhz;
++	unsigned char minreadperf_8b_52mhz;
++	unsigned char minwriteperf_8b_52mhz;
++	unsigned char reserved_11;
++	unsigned int sectorcount;
++	unsigned char reserved_12[288];
++	unsigned char supportedcommandsets;
++	unsigned char reserved_13[7];
++} mmc_extended_csd_reg_t;
++
++/* mmc sd responce */
++typedef struct {
++	unsigned int ocr;
++} mmc_resp_r3;
++
++typedef struct {
++	unsigned short cardstatus;
++	unsigned short newpublishedrca;
++} mmc_resp_r6;
++
++extern mmc_card_data mmc_dev;
++
++unsigned char mmc_lowlevel_init(void);
++unsigned char mmc_send_command(unsigned int cmd, unsigned int arg,
++			       unsigned int *response);
++unsigned char mmc_setup_clock(unsigned int iclk, unsigned short clkd);
++unsigned char mmc_set_opendrain(unsigned char state);
++unsigned char mmc_read_data(unsigned int *output_buf);
++
++#endif /* MMC_H */
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/mmc_host_def.h x-load-f243938/include/asm/arch-omap4/mmc_host_def.h
+--- x-load-f243938.orig/include/asm/arch-omap4/mmc_host_def.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/mmc_host_def.h	2012-06-07 14:45:39.453648667 -0300
+@@ -0,0 +1,168 @@
++/*
++ * (C) Copyright 2008
++ * Texas Instruments, <www.ti.com>
++ * Syed Mohammed Khasim <khasim@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation's version 2 of
++ * the License.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef MMC_HOST_DEFINITIONS_H
++#define MMC_HOST_DEFINITIONS_H
++
++#define OMAP_HSMMC1_BASE        0x4809C100
++#define OMAP_HSMMC2_BASE        0x480B4100
++
++/*
++ * OMAP HSMMC register definitions
++ */
++
++#define OMAP_HSMMC_SYSCONFIG	(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x010))
++#define OMAP_HSMMC_SYSSTATUS	(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x014))
++#define OMAP_HSMMC_CON		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x02C))
++#define OMAP_HSMMC_BLK		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x104))
++#define OMAP_HSMMC_ARG		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x108))
++#define OMAP_HSMMC_CMD		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x10C))
++#define OMAP_HSMMC_RSP10	(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x110))
++#define OMAP_HSMMC_RSP32	(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x114))
++#define OMAP_HSMMC_RSP54	(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x118))
++#define OMAP_HSMMC_RSP76	(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x11C))
++#define OMAP_HSMMC_DATA		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x120))
++#define OMAP_HSMMC_PSTATE	(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x124))
++#define OMAP_HSMMC_HCTL		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x128))
++#define OMAP_HSMMC_SYSCTL	(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x12C))
++#define OMAP_HSMMC_STAT		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x130))
++#define OMAP_HSMMC_IE		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x134))
++#define OMAP_HSMMC_CAPA		(*(volatile unsigned int *) (OMAP_HSMMC1_BASE+0x140))
++
++/* T2 Register definitions */
++#define CONTROL_PBIAS_LITE	(*(volatile unsigned int *) 0x4A100600)
++#define CONTROL_CONF_MMC1       (*(volatile unsigned int *) 0x4A100628)
++
++/*
++ * OMAP HS MMC Bit definitions
++ */
++#define MMC_SOFTRESET		(0x1 << 1)
++#define RESETDONE		(0x1 << 0)
++#define NOOPENDRAIN		(0x0 << 0)
++#define OPENDRAIN		(0x1 << 0)
++#define OD			(0x1 << 0)
++#define INIT_NOINIT		(0x0 << 1)
++#define INIT_INITSTREAM		(0x1 << 1)
++#define HR_NOHOSTRESP		(0x0 << 2)
++#define STR_BLOCK 		(0x0 << 3)
++#define MODE_FUNC		(0x0 << 4)
++#define DW8_1_4BITMODE 		(0x0 << 5)
++#define MIT_CTO			(0x0 << 6)
++#define CDP_ACTIVEHIGH		(0x0 << 7)
++#define WPP_ACTIVEHIGH 		(0x0 << 8)
++#define RESERVED_MASK		(0x3 << 9)
++#define CTPL_MMC_SD 		(0x0 << 11)
++#define BLEN_512BYTESLEN	(0x200 << 0)
++#define NBLK_STPCNT		(0x0 << 16)
++#define DE_DISABLE		(0x0 << 0)
++#define BCE_DISABLE		(0x0 << 1)
++#define ACEN_DISABLE		(0x0 << 2)
++#define DDIR_OFFSET		(4)
++#define DDIR_MASK		(0x1 << 4)
++#define DDIR_WRITE		(0x0 << 4)
++#define DDIR_READ		(0x1 << 4)
++#define MSBS_SGLEBLK		(0x0 << 5)
++#define RSP_TYPE_OFFSET		(16)
++#define RSP_TYPE_MASK		(0x3 << 16)
++#define RSP_TYPE_NORSP		(0x0 << 16)
++#define RSP_TYPE_LGHT136	(0x1 << 16)
++#define RSP_TYPE_LGHT48		(0x2 << 16)
++#define RSP_TYPE_LGHT48B	(0x3 << 16)
++#define CCCE_NOCHECK		(0x0 << 19)
++#define CCCE_CHECK		(0x1 << 19)
++#define CICE_NOCHECK		(0x0 << 20)
++#define CICE_CHECK		(0x1 << 20)
++#define DP_OFFSET		(21)
++#define DP_MASK			(0x1 << 21)
++#define DP_NO_DATA		(0x0 << 21)
++#define DP_DATA			(0x1 << 21)
++#define CMD_TYPE_NORMAL		(0x0 << 22)
++#define INDEX_OFFSET		(24)
++#define INDEX_MASK		(0x3f << 24)
++#define INDEX(i)		(i << 24)
++#define DATI_MASK		(0x1 << 1)
++#define DATI_CMDDIS		(0x1 << 1)
++#define DTW_1_BITMODE		(0x0 << 1)
++#define DTW_4_BITMODE		(0x1 << 1)
++#define SDBP_PWROFF		(0x0 << 8)
++#define SDBP_PWRON		(0x1 << 8)
++#define SDVS_1V8		(0x5 << 9)
++#define SDVS_3V0		(0x6 << 9)
++#define ICE_MASK		(0x1 << 0)
++#define ICE_STOP		(0x0 << 0)
++#define ICS_MASK		(0x1 << 1)
++#define ICS_NOTREADY		(0x0 << 1)
++#define ICE_OSCILLATE		(0x1 << 0)
++#define CEN_MASK		(0x1 << 2)
++#define CEN_DISABLE		(0x0 << 2)
++#define CEN_ENABLE		(0x1 << 2)
++#define CLKD_OFFSET		(6)
++#define CLKD_MASK		(0x3FF << 6)
++#define DTO_MASK		(0xF << 16)
++#define DTO_15THDTO		(0xE << 16)
++#define SOFTRESETALL		(0x1 << 24)
++#define CC_MASK			(0x1 << 0)
++#define TC_MASK			(0x1 << 1)
++#define BWR_MASK		(0x1 << 4)
++#define BRR_MASK		(0x1 << 5)
++#define ERRI_MASK		(0x1 << 15)
++#define IE_CC			(0x01 << 0)
++#define IE_TC			(0x01 << 1)
++#define IE_BWR			(0x01 << 4)
++#define IE_BRR			(0x01 << 5)
++#define IE_CTO			(0x01 << 16)
++#define IE_CCRC			(0x01 << 17)
++#define IE_CEB			(0x01 << 18)
++#define IE_CIE			(0x01 << 19)
++#define IE_DTO			(0x01 << 20)
++#define IE_DCRC			(0x01 << 21)
++#define IE_DEB			(0x01 << 22)
++#define IE_CERR			(0x01 << 28)
++#define IE_BADA			(0x01 << 29)
++
++#define VS30_3V0SUP		(1 << 25)
++#define VS18_1V8SUP		(1 << 26)
++
++/* Driver definitions */
++#define MMCSD_SECTOR_SIZE	(512)
++#define MMC_CARD		0
++#define SD_CARD			1
++#define BYTE_MODE		0
++#define SECTOR_MODE		1
++#define CLK_INITSEQ		0
++#define CLK_400KHZ		1
++#define CLK_MISC		2
++
++typedef struct {
++	unsigned int card_type;
++	unsigned int version;
++	unsigned int mode;
++	unsigned int size;
++	unsigned int RCA;
++} mmc_card_data;
++
++#define mmc_reg_out(addr, mask, val) \
++	(addr) = (((addr)) & (~(mask)) ) | ( (val) & (mask));
++
++#endif				/* MMC_HOST_DEFINITIONS_H */
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/mux.h x-load-f243938/include/asm/arch-omap4/mux.h
+--- x-load-f243938.orig/include/asm/arch-omap4/mux.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/mux.h	2012-06-07 14:45:39.457648667 -0300
+@@ -0,0 +1,392 @@
++/* Copyright 2009
++ * Texas Instruments, <www.ti.com>
++ * Syed Rafiuddin <rafiuddin.syed@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++#ifndef _OMAP4430_MUX_H_
++#define _OMAP4430_MUX_H_
++
++/*
++ * OFF_PD       - Off mode pull type down
++ * OFF_PU       - Off mode pull type up
++ * OFF_OUT_PTD  - Off Mode Mux low for OUT
++ * OFF_OUT_PTU  - Off Mode Mux high for OUT
++ * OFF_IN       - Off Mode Mux set to IN
++ * OFF_OUT      - Off Mode Mux set to OUT
++ * OFF_EN       - Off Mode Mux Enable
++ * IEN          - Input Enable
++ * IDIS         - Input Disable
++ * PTD          - Pull type Down
++ * PTU          - Pull type Up
++ * DIS          - Pull type selection is inactive
++ * EN           - Pull type selection is active
++ * M0           - Mode 0
++ */
++#ifdef CONFIG_OFF_PADCONF
++#define OFF_PD          (1 << 12)
++#define OFF_PU          (3 << 12)
++#define OFF_OUT_PTD     (0 << 10)
++#define OFF_OUT_PTU     (2 << 10)
++#define OFF_IN          (1 << 10)
++#define OFF_OUT         (0 << 10)
++#define OFF_EN          (1 << 9)
++#else
++#define OFF_PD          (0 << 12)
++#define OFF_PU          (0 << 12)
++#define OFF_OUT_PTD     (0 << 10)
++#define OFF_OUT_PTU     (0 << 10)
++#define OFF_IN          (0 << 10)
++#define OFF_OUT         (0 << 10)
++#define OFF_EN          (0 << 9)
++#endif
++
++#define IEN             (1 << 8)
++#define IDIS            (0 << 8)
++#define PTU             (3 << 3)
++#define PTD             (1 << 3)
++#define EN              (1 << 3)
++#define DIS             (0 << 3)
++
++#define M0              0
++#define M1              1
++#define M2              2
++#define M3              3
++#define M4              4
++#define M5              5
++#define M6              6
++#define M7              7
++
++#ifdef CONFIG_OFF_PADCONF
++#define OFF_IN_PD       (OFF_PD | OFF_IN | OFF_EN)
++#define OFF_IN_PU       (OFF_PU | OFF_IN | OFF_EN)
++#define OFF_OUT_PD      (OFF_OUT_PTD | OFF_OUT | OFF_EN)
++#define OFF_OUT_PU      (OFF_OUT_PTU | OFF_OUT | OFF_EN)
++#else
++#define OFF_IN_PD       0
++#define OFF_IN_PU       0
++#define OFF_OUT_PD      0
++#define OFF_OUT_PU      0
++#endif /* #ifdef CONFIG_OFF_PADCONF */
++
++/*
++ * To get the actual address the offset has to added
++ * with OMAP44XX_CTRL_BASE to get the actual address
++ */
++
++/* OMAP4 SPECIFIC PADCONF REGISTERS */
++
++#define CONTROL_PADCONF_CORE_REVISION		0x0000
++#define CONTROL_PADCONF_CORE_HWINFO		0x0004
++#define CONTROL_PADCONF_CORE_SYSCONFIG		0x0010
++#define CONTROL_PADCONF_GPMC_AD0		0x0040
++#define CONTROL_PADCONF_GPMC_AD1		0x0042
++#define CONTROL_PADCONF_GPMC_AD2		0x0044
++#define CONTROL_PADCONF_GPMC_AD3		0x0046
++#define CONTROL_PADCONF_GPMC_AD4		0x0048
++#define CONTROL_PADCONF_GPMC_AD5		0x004A
++#define CONTROL_PADCONF_GPMC_AD6		0x004C
++#define CONTROL_PADCONF_GPMC_AD7		0x004E
++#define CONTROL_PADCONF_GPMC_AD8		0x0050
++#define CONTROL_PADCONF_GPMC_AD9		0x0052
++#define CONTROL_PADCONF_GPMC_AD10		0x0054
++#define CONTROL_PADCONF_GPMC_AD11		0x0056
++#define CONTROL_PADCONF_GPMC_AD12		0x0058
++#define CONTROL_PADCONF_GPMC_AD13		0x005A
++#define CONTROL_PADCONF_GPMC_AD14		0x005C
++#define CONTROL_PADCONF_GPMC_AD15		0x005E
++#define CONTROL_PADCONF_GPMC_A16		0x0060
++#define CONTROL_PADCONF_GPMC_A17		0x0062
++#define CONTROL_PADCONF_GPMC_A18		0x0064
++#define CONTROL_PADCONF_GPMC_A19		0x0066
++#define CONTROL_PADCONF_GPMC_A20		0x0068
++#define CONTROL_PADCONF_GPMC_A21		0x006A
++#define CONTROL_PADCONF_GPMC_A22		0x006C
++#define CONTROL_PADCONF_GPMC_A23		0x006E
++#define CONTROL_PADCONF_GPMC_A24		0x0070
++#define CONTROL_PADCONF_GPMC_A25		0x0072
++#define CONTROL_PADCONF_GPMC_NCS0		0x0074
++#define CONTROL_PADCONF_GPMC_NCS1		0x0076
++#define CONTROL_PADCONF_GPMC_NCS2		0x0078
++#define CONTROL_PADCONF_GPMC_NCS3		0x007A
++#define CONTROL_PADCONF_GPMC_NWP		0x007C
++#define CONTROL_PADCONF_GPMC_CLK		0x007E
++#define CONTROL_PADCONF_GPMC_NADV_ALE		0x0080
++#define CONTROL_PADCONF_GPMC_NOE		0x0082
++#define CONTROL_PADCONF_GPMC_NWE		0x0084
++#define CONTROL_PADCONF_GPMC_NBE0_CLE		0x0086
++#define CONTROL_PADCONF_GPMC_NBE1		0x0088
++#define CONTROL_PADCONF_GPMC_WAIT0		0x008A
++#define CONTROL_PADCONF_GPMC_WAIT1		0x008C
++#define CONTROL_PADCONF_C2C_DATA11		0x008E
++#define CONTROL_PADCONF_C2C_DATA12		0x0090
++#define CONTROL_PADCONF_C2C_DATA13		0x0092
++#define CONTROL_PADCONF_C2C_DATA14		0x0094
++#define CONTROL_PADCONF_C2C_DATA15		0x0096
++#define CONTROL_PADCONF_HDMI_HPD		0x0098
++#define CONTROL_PADCONF_HDMI_CEC		0x009A
++#define CONTROL_PADCONF_HDMI_DDC_SCL		0x009C
++#define CONTROL_PADCONF_HDMI_DDC_SDA		0x009E
++#define CONTROL_PADCONF_CSI21_DX0		0x00A0
++#define CONTROL_PADCONF_CSI21_DY0		0x00A2
++#define CONTROL_PADCONF_CSI21_DX1		0x00A4
++#define CONTROL_PADCONF_CSI21_DY1		0x00A6
++#define CONTROL_PADCONF_CSI21_DX2		0x00A8
++#define CONTROL_PADCONF_CSI21_DY2		0x00AA
++#define CONTROL_PADCONF_CSI21_DX3		0x00AC
++#define CONTROL_PADCONF_CSI21_DY3		0x00AE
++#define CONTROL_PADCONF_CSI21_DX4		0x00B0
++#define CONTROL_PADCONF_CSI21_DY4		0x00B2
++#define CONTROL_PADCONF_CSI22_DX0		0x00B4
++#define CONTROL_PADCONF_CSI22_DY0		0x00B6
++#define CONTROL_PADCONF_CSI22_DX1		0x00B8
++#define CONTROL_PADCONF_CSI22_DY1		0x00BA
++#define CONTROL_PADCONF_CAM_SHUTTER		0x00BC
++#define CONTROL_PADCONF_CAM_STROBE		0x00BE
++#define CONTROL_PADCONF_CAM_GLOBALRESET		0x00C0
++#define CONTROL_PADCONF_USBB1_ULPITLL_CLK	0x00C2
++#define CONTROL_PADCONF_USBB1_ULPITLL_STP	0x00C4
++#define CONTROL_PADCONF_USBB1_ULPITLL_DIR	0x00C6
++#define CONTROL_PADCONF_USBB1_ULPITLL_NXT	0x00C8
++#define CONTROL_PADCONF_USBB1_ULPITLL_DAT0	0x00CA
++#define CONTROL_PADCONF_USBB1_ULPITLL_DAT1	0x00CC
++#define CONTROL_PADCONF_USBB1_ULPITLL_DAT2	0x00CE
++#define CONTROL_PADCONF_USBB1_ULPITLL_DAT3	0x00D0
++#define CONTROL_PADCONF_USBB1_ULPITLL_DAT4	0x00D2
++#define CONTROL_PADCONF_USBB1_ULPITLL_DAT5	0x00D4
++#define CONTROL_PADCONF_USBB1_ULPITLL_DAT6	0x00D6
++#define CONTROL_PADCONF_USBB1_ULPITLL_DAT7	0x00D8
++#define CONTROL_PADCONF_USBB1_HSIC_DATA		0x00DA
++#define CONTROL_PADCONF_USBB1_HSIC_STROBE	0x00DC
++#define CONTROL_PADCONF_USBC1_ICUSB_DP		0x00DE
++#define CONTROL_PADCONF_USBC1_ICUSB_DM		0x00E0
++#define CONTROL_PADCONF_SDMMC1_CLK		0x00E2
++#define CONTROL_PADCONF_SDMMC1_CMD		0x00E4
++#define CONTROL_PADCONF_SDMMC1_DAT0		0x00E6
++#define CONTROL_PADCONF_SDMMC1_DAT1		0x00E8
++#define CONTROL_PADCONF_SDMMC1_DAT2		0x00EA
++#define CONTROL_PADCONF_SDMMC1_DAT3		0x00EC
++#define CONTROL_PADCONF_SDMMC1_DAT4		0x00EE
++#define CONTROL_PADCONF_SDMMC1_DAT5		0x00F0
++#define CONTROL_PADCONF_SDMMC1_DAT6		0x00F2
++#define CONTROL_PADCONF_SDMMC1_DAT7		0x00F4
++#define CONTROL_PADCONF_ABE_MCBSP2_CLKX		0x00F6
++#define CONTROL_PADCONF_ABE_MCBSP2_DR		0x00F8
++#define CONTROL_PADCONF_ABE_MCBSP2_DX		0x00FA
++#define CONTROL_PADCONF_ABE_MCBSP2_FSX		0x00FC
++#define CONTROL_PADCONF_ABE_MCBSP1_CLKX		0x00FE
++#define CONTROL_PADCONF_ABE_MCBSP1_DR		0x0100
++#define CONTROL_PADCONF_ABE_MCBSP1_DX		0x0102
++#define CONTROL_PADCONF_ABE_MCBSP1_FSX		0x0104
++#define CONTROL_PADCONF_ABE_PDM_UL_DATA		0x0106
++#define CONTROL_PADCONF_ABE_PDM_DL_DATA		0x0108
++#define CONTROL_PADCONF_ABE_PDM_FRAME		0x010A
++#define CONTROL_PADCONF_ABE_PDM_LB_CLK		0x010C
++#define CONTROL_PADCONF_ABE_CLKS		0x010E
++#define CONTROL_PADCONF_ABE_DMIC_CLK1		0x0110
++#define CONTROL_PADCONF_ABE_DMIC_DIN1		0x0112
++#define CONTROL_PADCONF_ABE_DMIC_DIN2		0x0114
++#define CONTROL_PADCONF_ABE_DMIC_DIN3		0x0116
++#define CONTROL_PADCONF_UART2_CTS		0x0118
++#define CONTROL_PADCONF_UART2_RTS		0x011A
++#define CONTROL_PADCONF_UART2_RX		0x011C
++#define CONTROL_PADCONF_UART2_TX		0x011E
++#define CONTROL_PADCONF_HDQ_SIO			0x0120
++#define CONTROL_PADCONF_I2C1_SCL		0x0122
++#define CONTROL_PADCONF_I2C1_SDA		0x0124
++#define CONTROL_PADCONF_I2C2_SCL		0x0126
++#define CONTROL_PADCONF_I2C2_SDA		0x0128
++#define CONTROL_PADCONF_I2C3_SCL		0x012A
++#define CONTROL_PADCONF_I2C3_SDA		0x012C
++#define CONTROL_PADCONF_I2C4_SCL		0x012E
++#define CONTROL_PADCONF_I2C4_SDA		0x0130
++#define CONTROL_PADCONF_MCSPI1_CLK		0x0132
++#define CONTROL_PADCONF_MCSPI1_SOMI		0x0134
++#define CONTROL_PADCONF_MCSPI1_SIMO		0x0136
++#define CONTROL_PADCONF_MCSPI1_CS0		0x0138
++#define CONTROL_PADCONF_MCSPI1_CS1		0x013A
++#define CONTROL_PADCONF_MCSPI1_CS2		0x013C
++#define CONTROL_PADCONF_MCSPI1_CS3		0x013E
++#define CONTROL_PADCONF_UART3_CTS_RCTX		0x0140
++#define CONTROL_PADCONF_UART3_RTS_SD		0x0142
++#define CONTROL_PADCONF_UART3_RX_IRRX		0x0144
++#define CONTROL_PADCONF_UART3_TX_IRTX		0x0146
++#define CONTROL_PADCONF_SDMMC5_CLK		0x0148
++#define CONTROL_PADCONF_SDMMC5_CMD		0x014A
++#define CONTROL_PADCONF_SDMMC5_DAT0		0x014C
++#define CONTROL_PADCONF_SDMMC5_DAT1		0x014E
++#define CONTROL_PADCONF_SDMMC5_DAT2		0x0150
++#define CONTROL_PADCONF_SDMMC5_DAT3		0x0152
++#define CONTROL_PADCONF_MCSPI4_CLK		0x0154
++#define CONTROL_PADCONF_MCSPI4_SIMO		0x0156
++#define CONTROL_PADCONF_MCSPI4_SOMI		0x0158
++#define CONTROL_PADCONF_MCSPI4_CS0		0x015A
++#define CONTROL_PADCONF_UART4_RX		0x015C
++#define CONTROL_PADCONF_UART4_TX		0x015E
++#define CONTROL_PADCONF_USBB2_ULPITLL_CLK	0x0160
++#define CONTROL_PADCONF_USBB2_ULPITLL_STP	0x0162
++#define CONTROL_PADCONF_USBB2_ULPITLL_DIR	0x0164
++#define CONTROL_PADCONF_USBB2_ULPITLL_NXT	0x0166
++#define CONTROL_PADCONF_USBB2_ULPITLL_DAT0	0x0168
++#define CONTROL_PADCONF_USBB2_ULPITLL_DAT1	0x016A
++#define CONTROL_PADCONF_USBB2_ULPITLL_DAT2	0x016C
++#define CONTROL_PADCONF_USBB2_ULPITLL_DAT3	0x016E
++#define CONTROL_PADCONF_USBB2_ULPITLL_DAT4	0x0170
++#define CONTROL_PADCONF_USBB2_ULPITLL_DAT5	0x0172
++#define CONTROL_PADCONF_USBB2_ULPITLL_DAT6	0x0174
++#define CONTROL_PADCONF_USBB2_ULPITLL_DAT7	0x0176
++#define CONTROL_PADCONF_USBB2_HSIC_DATA		0x0178
++#define CONTROL_PADCONF_USBB2_HSIC_STROBE	0x017A
++#define CONTROL_PADCONF_UNIPRO_TX0		0x017C
++#define CONTROL_PADCONF_UNIPRO_TY0		0x017E
++#define CONTROL_PADCONF_UNIPRO_TX1		0x0180
++#define CONTROL_PADCONF_UNIPRO_TY1		0x0182
++#define CONTROL_PADCONF_UNIPRO_TX2		0x0184
++#define CONTROL_PADCONF_UNIPRO_TY2		0x0186
++#define CONTROL_PADCONF_UNIPRO_RX0		0x0188
++#define CONTROL_PADCONF_UNIPRO_RY0		0x018A
++#define CONTROL_PADCONF_UNIPRO_RX1		0x018C
++#define CONTROL_PADCONF_UNIPRO_RY1		0x018E
++#define CONTROL_PADCONF_UNIPRO_RX2		0x0190
++#define CONTROL_PADCONF_UNIPRO_RY2		0x0192
++#define CONTROL_PADCONF_USBA0_OTG_CE		0x0194
++#define CONTROL_PADCONF_USBA0_OTG_DP		0x0196
++#define CONTROL_PADCONF_USBA0_OTG_DM		0x0198
++#define CONTROL_PADCONF_FREF_CLK1_OUT		0x019A
++#define CONTROL_PADCONF_FREF_CLK2_OUT		0x019C
++#define CONTROL_PADCONF_SYS_NIRQ1		0x019E
++#define CONTROL_PADCONF_SYS_NIRQ2		0x01A0
++#define CONTROL_PADCONF_SYS_BOOT0		0x01A2
++#define CONTROL_PADCONF_SYS_BOOT1		0x01A4
++#define CONTROL_PADCONF_SYS_BOOT2		0x01A6
++#define CONTROL_PADCONF_SYS_BOOT3		0x01A8
++#define CONTROL_PADCONF_SYS_BOOT4		0x01AA
++#define CONTROL_PADCONF_SYS_BOOT5		0x01AC
++#define CONTROL_PADCONF_DPM_EMU0		0x01AE
++#define CONTROL_PADCONF_DPM_EMU1		0x01B0
++#define CONTROL_PADCONF_DPM_EMU2		0x01B2
++#define CONTROL_PADCONF_DPM_EMU3		0x01B4
++#define CONTROL_PADCONF_DPM_EMU4		0x01B6
++#define CONTROL_PADCONF_DPM_EMU5		0x01B8
++#define CONTROL_PADCONF_DPM_EMU6		0x01BA
++#define CONTROL_PADCONF_DPM_EMU7		0x01BC
++#define CONTROL_PADCONF_DPM_EMU8		0x01BE
++#define CONTROL_PADCONF_DPM_EMU9		0x01C0
++#define CONTROL_PADCONF_DPM_EMU10		0x01C2
++#define CONTROL_PADCONF_DPM_EMU11		0x01C4
++#define CONTROL_PADCONF_DPM_EMU12		0x01C6
++#define CONTROL_PADCONF_DPM_EMU13		0x01C8
++#define CONTROL_PADCONF_DPM_EMU14		0x01CA
++#define CONTROL_PADCONF_DPM_EMU15		0x01CC
++#define CONTROL_PADCONF_DPM_EMU16		0x01CE
++#define CONTROL_PADCONF_DPM_EMU17		0x01D0
++#define CONTROL_PADCONF_DPM_EMU18		0x01D2
++#define CONTROL_PADCONF_DPM_EMU19		0x01D4
++#define CONTROL_PADCONF_WAKEUPEVENT_0		0x01D8
++#define CONTROL_PADCONF_WAKEUPEVENT_1		0x01DC
++#define CONTROL_PADCONF_WAKEUPEVENT_2		0x01E0
++#define CONTROL_PADCONF_WAKEUPEVENT_3		0x01E4
++#define CONTROL_PADCONF_WAKEUPEVENT_4		0x01E8
++#define CONTROL_PADCONF_WAKEUPEVENT_5		0x01EC
++#define CONTROL_PADCONF_WAKEUPEVENT_6		0x01F0
++
++#define CONTROL_PADCONF_GLOBAL			0x05A2
++#define CONTROL_PADCONF_MODE			0x05A4
++#define CONTROL_SMART1IO_PADCONF_0		0x05A8
++#define CONTROL_SMART1IO_PADCONF_1		0x05AC
++#define CONTROL_SMART2IO_PADCONF_0		0x05B0
++#define CONTROL_SMART2IO_PADCONF_1		0x05B4
++#define CONTROL_SMART3IO_PADCONF_0		0x05B8
++#define CONTROL_SMART3IO_PADCONF_1		0x05BC
++#define CONTROL_SMART3IO_PADCONF_2		0x05C0
++#define CONTROL_USBB_HSIC			0x05C4
++#define CONTROL_SLIMBUS				0x05C8
++#define CONTROL_PBIASLITE			0x0600
++#define CONTROL_I2C_0				0x0604
++#define CONTROL_CAMERA_RX			0x0608
++#define CONTROL_AVDAC				0x060C
++#define CONTROL_HDMI_TX_PHY			0x0610
++#define CONTROL_MMC2				0x0614
++#define CONTROL_DSIPHY				0x0618
++#define CONTROL_MCBSPLP				0x061C
++#define CONTROL_USB2PHYCORE			0x0620
++#define CONTROL_I2C_1				0x0624
++#define CONTROL_MMC1				0x0628
++#define CONTROL_HSI				0x062C
++#define CONTROL_USB				0x0630
++#define CONTROL_HDQ				0x0634
++#define CONTROL_LPDDR2IO1_0			0x0638
++#define CONTROL_LPDDR2IO1_1			0x063C
++#define CONTROL_LPDDR2IO1_2			0x0640
++#define CONTROL_LPDDR2IO1_3			0x0644
++#define CONTROL_LPDDR2IO2_0			0x0648
++#define CONTROL_LPDDR2IO2_1			0x064C
++#define CONTROL_LPDDR2IO2_2			0x0650
++#define CONTROL_LPDDR2IO2_3			0x0654
++#define CONTROL_BUS_HOLD			0x0658
++#define CONTROL_C2C				0x065C
++#define CONTROL_CORE_CONTROL_SPARE_RW		0x0660
++#define CONTROL_CORE_CONTROL_SPARE_R		0x0664
++#define CONTROL_CORE_CONTROL_SPARE_R_C0		0x0668
++#define CONTROL_EFUSE_1				0x0700
++#define CONTROL_EFUSE_2				0x0704
++#define CONTROL_EFUSE_3				0x0708
++#define CONTROL_EFUSE_4				0x070C
++
++#define CONTROL_PADCONF_WKUP_REVISION		0x0000
++#define CONTROL_PADCONF_WKUP_HWINFO		0x0004
++#define CONTROL_PADCONF_WKUP_SYSCONFIG		0x0010
++#define CONTROL_WKUP_PAD0_SIM_IO		0x0040
++#define CONTROL_WKUP_PAD1_SIM_CLK		0x0042
++#define CONTROL_WKUP_PAD0_SIM_RESET		0x0044
++#define CONTROL_WKUP_PAD1_SIM_CD		0x0046
++#define CONTROL_WKUP_PAD0_SIM_PWRCTRL		0x0048
++#define CONTROL_WKUP_PAD1_SR_SCL		0x004A
++#define CONTROL_WKUP_PAD0_SR_SDA		0x004C
++#define CONTROL_WKUP_PAD1_FREF_XTAL_IN		0x004E
++#define CONTROL_WKUP_PAD0_FREF_SLICER_IN	0x0050
++#define CONTROL_WKUP_PAD1_FREF_CLK_IOREQ	0x0052
++#define CONTROL_WKUP_PAD0_FREF_CLK0_OUT		0x0054
++#define CONTROL_WKUP_PAD1_FREF_CLK3_REQ		0x0056
++#define CONTROL_WKUP_PAD0_FREF_CLK3_OUT		0x0058
++#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ		0x005A
++#define CONTROL_WKUP_PAD0_FREF_CLK4_OUT		0x005C
++#define CONTROL_WKUP_PAD1_SYS_32K		0x005E
++#define CONTROL_WKUP_PAD0_SYS_NRESPWRON		0x0060
++#define CONTROL_WKUP_PAD1_SYS_NRESWARM		0x0062
++#define CONTROL_WKUP_PAD0_SYS_PWR_REQ		0x0064
++#define CONTROL_WKUP_PAD1_SYS_PWRON_RESET	0x0066
++#define CONTROL_WKUP_PAD0_SYS_BOOT6		0x0068
++#define CONTROL_WKUP_PAD1_SYS_BOOT7		0x006A
++#define CONTROL_WKUP_PAD0_JTAG_NTRST		0x006C
++#define CONTROL_WKUP_PAD1_JTAG_TCK		0x006D
++#define CONTROL_WKUP_PAD0_JTAG_RTCK		0x0070
++#define CONTROL_WKUP_PAD1_JTAG_TMS_TMSC		0x0072
++#define CONTROL_WKUP_PAD0_JTAG_TDI		0x0074
++#define CONTROL_WKUP_PAD1_JTAG_TDO		0x0076
++#define CONTROL_PADCONF_WAKEUPEVENT_0		0x007C
++#define CONTROL_SMART1NOPMIO_PADCONF_0		0x05A0
++#define CONTROL_SMART1NOPMIO_PADCONF_1		0x05A4
++#define CONTROL_PADCONF_MODE			0x05A8
++#define CONTROL_XTAL_OSCILLATOR			0x05AC
++#define CONTROL_CONTROL_I2C_2			0x0604
++#define CONTROL_CONTROL_JTAG			0x0608
++#define CONTROL_CONTROL_SYS			0x060C
++#define CONTROL_WKUP_CONTROL_SPARE_RW		0x0614
++#define CONTROL_WKUP_CONTROL_SPARE_R		0x0618
++#define CONTROL_WKUP_CONTROL_SPARE_R_C0		0x061C
++
++#endif
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/omap4430.h x-load-f243938/include/asm/arch-omap4/omap4430.h
+--- x-load-f243938.orig/include/asm/arch-omap4/omap4430.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/omap4430.h	2012-06-07 14:45:39.457648667 -0300
+@@ -0,0 +1,137 @@
++/*
++ * (C) Copyright 2006-2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ * Syed Mohammed Khasim <x0khasim@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef _OMAP4430_SYS_H_
++#define _OMAP4430_SYS_H_
++
++#include <asm/arch/sizes.h>
++
++/*
++ * 4430 specific Section
++ */
++
++/* Stuff on L3 Interconnect */
++#define SMX_APE_BASE			0x68000000
++
++/* L3 Firewall */
++#define A_REQINFOPERM0		(SMX_APE_BASE + 0x05048)
++#define A_READPERM0		(SMX_APE_BASE + 0x05050)
++#define A_WRITEPERM0		(SMX_APE_BASE + 0x05058)
++
++/* GPMC */
++#define OMAP44XX_GPMC_BASE		(0x50000000)
++
++/* DMM */
++#define OMAP44XX_DMM_BASE		0x4E000000
++
++/* SMS */
++#define OMAP44XX_SMS_BASE               0x6C000000
++
++/* SDRC */
++#define OMAP44XX_SDRC_BASE              0x6D000000
++
++
++/*
++ * L4 Peripherals - L4 Wakeup and L4 Core now
++ */
++#define OMAP44XX_CORE_L4_IO_BASE	0x4A000000
++
++#define OMAP44XX_WAKEUP_L4_IO_BASE	0x4A300000
++
++#define OMAP44XX_L4_PER			0x48000000
++
++#define OMAP44XX_L4_IO_BASE		OMAP44XX_CORE_L4_IO_BASE
++
++/* CONTROL */
++//#define OMAP44XX_CTRL_BASE		(OMAP44XX_L4_IO_BASE+0x2000)
++#define OMAP44XX_CTRL_BASE		0x4a100000
++
++/* TAP information  dont know for 3430*/
++#define OMAP44XX_TAP_BASE	(0x49000000) /*giving some junk for virtio */
++
++/* UART */
++#define OMAP44XX_UART1			(OMAP44XX_L4_PER+0x6a000)
++#define OMAP44XX_UART2			(OMAP44XX_L4_PER+0x6c000)
++#define OMAP44XX_UART3			(OMAP44XX_L4_PER+0x20000)
++
++/* General Purpose Timers */
++#define OMAP44XX_GPT1			0x48318000
++#define OMAP44XX_GPT2			0x48032000
++#define OMAP44XX_GPT3			0x48034000
++#define OMAP44XX_GPT4			0x48036000
++#define OMAP44XX_GPT5			0x40138000
++#define OMAP44XX_GPT6			0x4013A000
++#define OMAP44XX_GPT7			0x4013C000
++#define OMAP44XX_GPT8			0x4013E000
++#define OMAP44XX_GPT9			0x48040000
++#define OMAP44XX_GPT10			0x48086000
++#define OMAP44XX_GPT11			0x48088000
++#define OMAP44XX_GPT12			0x48304000
++
++/* WatchDog Timers (1 secure, 3 GP) */
++#define WD1_BASE			(0x4A322000)
++#define WD2_BASE			(0x4A314000)
++#define WD3_BASE			(0x40130000)
++
++/* 32KTIMER */
++#define SYNC_32KTIMER_BASE		(0x48320000)
++#define S32K_CR				(SYNC_32KTIMER_BASE+0x10)
++
++/*
++ * SDP4430 specific Section
++ */
++
++/*
++ *  The 443x's chip selects are programmable.  The mask ROM
++ *  does configure CS0 to 0x08000000 before dispatch.  So, if
++ *  you want your code to live below that address, you have to
++ *  be prepared to jump though hoops, to reset the base address.
++ *  Same as in SDP4430
++ */
++#ifdef CONFIG_OMAP44XX
++/* base address for indirect vectors (internal boot mode) */
++#define SRAM_OFFSET0                    0x40000000
++#define SRAM_OFFSET1                    0x00300000
++#define SRAM_OFFSET2                    0x0000D000
++#define SRAM_OFFSET3                    0x00000800
++#define SRAM_VECT_CODE                  (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2|SRAM_OFFSET3)
++#define LOW_LEVEL_SRAM_STACK            0x4030DFFC
++#endif
++
++#if defined(CONFIG_4430SDP)
++/* FPGA on Debug board.*/
++# define ETH_CONTROL_REG			(DEBUG_BASE+0x30b)
++# define LAN_RESET_REGISTER		(DEBUG_BASE+0x1c)
++
++# define DIP_SWITCH_INPUT_REG2		(DEBUG_BASE+0x60)
++# define LED_REGISTER			(DEBUG_BASE+0x40)
++# define FPGA_REV_REGISTER		(DEBUG_BASE+0x10)
++# define EEPROM_MAIN_BRD			(DEBUG_BASE+0x10000+0x1800)
++# define EEPROM_CONN_BRD			(DEBUG_BASE+0x10000+0x1900)
++# define EEPROM_UI_BRD			(DEBUG_BASE+0x10000+0x1A00)
++# define EEPROM_MCAM_BRD			(DEBUG_BASE+0x10000+0x1B00)
++# define ENHANCED_UI_EE_NAME		"750-2075"
++#endif
++
++#endif  /* _OMAP4430_SYS_H_ */
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/rev.h x-load-f243938/include/asm/arch-omap4/rev.h
+--- x-load-f243938.orig/include/asm/arch-omap4/rev.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/rev.h	2012-06-07 14:45:39.457648667 -0300
+@@ -0,0 +1,41 @@
++/*
++ * (C) Copyright 2006-2009
++ * Texas Instruments, <www.ti.com>
++ *
++ * Richard Woodruff <r-woodruff2@ti.com>
++ * Syed Mohammed Khasim <x0khasim@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef _OMAP44XX_REV_H_
++#define _OMAP44XX_REV_H_
++
++#define CDB_DDR_COMBO                   /* combo part on cpu daughter card */
++#define CDB_DDR_IPDB                    /* 2x16 parts on daughter card */
++
++#define DDR_100		100             /* type found on most mem d-boards */
++#define DDR_111		111             /* some combo parts */
++#define DDR_133		133             /* most combo, some mem d-boards */
++#define DDR_165		165             /* future parts */
++
++#define CPU_4430	0x4430
++
++#define CPU_4430_ES1	1
++
++#endif
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/sizes.h x-load-f243938/include/asm/arch-omap4/sizes.h
+--- x-load-f243938.orig/include/asm/arch-omap4/sizes.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/sizes.h	2012-06-07 14:45:39.457648667 -0300
+@@ -0,0 +1,48 @@
++/*
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
++ */
++/*  Size defintions
++ *  Copyright (C) ARM Limited 1998. All rights reserved.
++ */
++
++#ifndef __sizes_h
++#define __sizes_h			1
++
++/* handy sizes */
++#define SZ_1K				0x00000400
++#define SZ_4K				0x00001000
++#define SZ_8K				0x00002000
++#define SZ_16K				0x00004000
++#define SZ_32K				0x00008000
++#define SZ_64K				0x00010000
++#define SZ_128K				0x00020000
++#define SZ_256K				0x00040000
++#define SZ_512K				0x00080000
++
++#define SZ_1M				0x00100000
++#define SZ_2M				0x00200000
++#define SZ_4M				0x00400000
++#define SZ_8M				0x00800000
++#define SZ_16M				0x01000000
++#define SZ_31M				0x01F00000
++#define SZ_32M				0x02000000
++#define SZ_64M				0x04000000
++#define SZ_128M				0x08000000
++#define SZ_256M				0x10000000
++#define SZ_512M				0x20000000
++
++#define SZ_1G				0x40000000
++#define SZ_2G				0x80000000
++
++#endif	/* __sizes_h */
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/sys_info.h x-load-f243938/include/asm/arch-omap4/sys_info.h
+--- x-load-f243938.orig/include/asm/arch-omap4/sys_info.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/sys_info.h	2012-06-07 14:45:39.457648667 -0300
+@@ -0,0 +1,75 @@
++/*
++ * (C) Copyright 2006-2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef _OMAP44XX_SYS_INFO_H_
++#define _OMAP44XX_SYS_INFO_H_
++
++#define XDR_POP		5      /* package on package part */
++#define SDR_DISCRETE	4      /* 128M memory SDR module*/
++#define DDR_STACKED	3      /* stacked part on 2422 */
++#define DDR_COMBO	2      /* combo part on cpu daughter card (menalaeus) */
++#define DDR_DISCRETE	1      /* 2x16 parts on daughter card */
++
++#define DDR_100		100    /* type found on most mem d-boards */
++#define DDR_111		111    /* some combo parts */
++#define DDR_133		133    /* most combo, some mem d-boards */
++#define DDR_165		165    /* future parts */
++
++#define CPU_4430	0x4430
++
++/* 343x real hardware:
++ *  ES1     = rev 0
++ */
++
++/* 343x code defines:
++ * ES1     = 0+1 = 1
++ * ES1     = 1+1 = 1
++ */
++#define CPU_4430_ES1		1
++
++/* Currently Virtio models this one */
++#define CPU_4430_CHIPID		0x0B68A000
++
++#define GPMC_MUXED		1
++#define GPMC_NONMUXED		0
++
++#define TYPE_NAND		0x800	/* bit pos for nand in gpmc reg */
++#define TYPE_NOR		0x000
++#define TYPE_ONENAND		0x800
++
++#define WIDTH_8BIT		0x0000
++#define WIDTH_16BIT		0x1000	/* bit pos for 16 bit in gpmc */
++
++#define I2C_MENELAUS		0x72	/* i2c id for companion chip */
++#define I2C_TRITON2		0x4B	/* addres of power group */
++
++#define BOOT_FAST_XIP		0x1f
++
++/* SDP definitions according to FPGA Rev. Is this OK?? */
++#define SDP_4430_VIRTIO		0x1
++#define SDP_4430_V1		0x2
++
++#define BOARD_4430_LABRADOR	0x80
++#define BOARD_4430_LABRADOR_V1	0x1
++
++#endif
+diff -uNr x-load-f243938.orig/include/asm/arch-omap4/sys_proto.h x-load-f243938/include/asm/arch-omap4/sys_proto.h
+--- x-load-f243938.orig/include/asm/arch-omap4/sys_proto.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/asm/arch-omap4/sys_proto.h	2012-06-07 14:45:39.457648667 -0300
+@@ -0,0 +1,60 @@
++/*
++ * (C) Copyright 2004-2009
++ * Texas Instruments, <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * version 2 as published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++  */
++#ifndef _OMAP44XX_SYS_PROTO_H_
++#define _OMAP44XX_SYS_PROTO_H_
++
++void prcm_init(void);
++void per_clocks_enable(void);
++void configure_core_dpll_no_lock(void);
++void lock_core_dpll(void);
++void lock_core_dpll_shadow(void);
++
++void memif_init(void);
++void sdrc_init(void);
++void do_sdrc_init(u32, u32);
++void gpmc_init(void);
++
++void ether_init(void);
++void watchdog_init(void);
++void set_muxconf_regs(void);
++
++u32 get_cpu_type(void);
++u32 get_cpu_rev(void);
++u32 get_mem_type(void);
++u32 get_sysboot_value(void);
++u32 get_gpmc0_base(void);
++u32 is_gpmc_muxed(void);
++u32 get_gpmc0_type(void);
++u32 get_gpmc0_width(void);
++u32 get_board_type(void);
++void display_board_info(u32);
++void update_mux(u32, u32);
++u32 get_sdr_cs_size(u32 offset);
++u32 running_in_sdram(void);
++u32 running_in_sram(void);
++u32 running_in_flash(void);
++u32 running_from_internal_boot(void);
++u32 get_device_type(void);
++
++void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value);
++u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound);
++void sdelay(unsigned long loops);
++
++#endif
+diff -uNr x-load-f243938.orig/include/configs/omap3530beagle.h x-load-f243938/include/configs/omap3530beagle.h
+--- x-load-f243938.orig/include/configs/omap3530beagle.h	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/include/configs/omap3530beagle.h	2012-06-07 15:17:38.625692457 -0300
+@@ -28,8 +28,8 @@
+ #define __CONFIG_H
+ 
+ /* serial printf facility takes about 3.5K */
+-#define CFG_PRINTF 
+-//#undef CFG_PRINTF 
++//#define CFG_PRINTF 
++#undef CFG_PRINTF 
+ 
+ /*
+  * High Level Configuration Options
+diff -uNr x-load-f243938.orig/include/configs/omap4430panda.h x-load-f243938/include/configs/omap4430panda.h
+--- x-load-f243938.orig/include/configs/omap4430panda.h	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/include/configs/omap4430panda.h	2012-06-07 14:45:39.457648667 -0300
+@@ -0,0 +1,106 @@
++/*
++ * (C) Copyright 2006 
++ * Texas Instruments <www.ti.com>
++ * Richard Woodruff <r-woodruff2@ti.com>
++ *
++ * X-Loader Configuation settings for the TI OMAP SDP3430 board.
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __CONFIG_H
++#define __CONFIG_H
++
++/* serial printf facility takes about 3.5K */
++#define CFG_PRINTF 
++//#undef CFG_PRINTF 
++
++/*
++ * High Level Configuration Options
++ */
++#define CONFIG_ARMCORTEXA9       1    /* This is an ARM V7 CPU core */
++#define CONFIG_OMAP              1    /* in a TI OMAP core */
++#define CONFIG_OMAP44XX          1    /* which is a 34XX */
++#define CONFIG_OMAP4430          1    /* which is in a 3430 */
++#define CONFIG_4430PANDA         1    /* working with SDP */
++
++/* Keep Default @ 33MHz at boot loader level
++ * On Phoenix board vlotage needs to be bumped up
++ * before scaling the MPU up
++ */
++#define CONFIG_MPU_600		1
++#define CORE_190MHZ		1
++/* Enable the below macro if MMC boot support is required */
++#define CONFIG_MMC               1
++#if defined(CONFIG_MMC)
++	/* To Enable MMC boot for OMAP4430 Panda */
++	//#define CONFIG_MMC1		1
++	/* To Enable EMMC boot for OMAP4430 Panda */
++	#define CONFIG_MMC2		1
++	#define CFG_CMD_MMC		1
++	#define CFG_CMD_FAT		1
++#endif
++
++#include <asm/arch/cpu.h>        /* get chip and board defs */
++
++/* uncomment it if you need timer based udelay(). it takes about 250 bytes */
++//#define CFG_UDELAY
++ 
++/* Clock Defines */
++#define V_OSCK                   19200000  /* Clock output from T2 */
++#define V_SCLK                   V_OSCK
++
++/* Memory type */
++#define CFG_4430SDRAM_DDR        1
++
++#ifdef CFG_PRINTF
++
++#define CFG_NS16550
++#define CFG_NS16550_SERIAL
++#define CFG_NS16550_REG_SIZE     (-4)
++#define CFG_NS16550_CLK          (48000000)
++#define CFG_NS16550_COM3         OMAP44XX_UART3
++ 
++/*
++ * select serial console configuration
++ */
++#define CONFIG_SERIAL1           1    /* UART1 on 3430SDP */
++#define CONFIG_CONS_INDEX        3
++
++#define CONFIG_BAUDRATE          115200
++#define CFG_PBSIZE               256
++
++#endif /* CFG_PRINTF */
++
++/*
++ * Miscellaneous configurable options
++ */
++#define CFG_LOADADDR             0x80e80000
++  
++#undef	CFG_CLKS_IN_HZ		/* everything, incl board info, in Hz */
++#define CFG_ENV_SIZE		0x100 
++/*-----------------------------------------------------------------------
++ * Stack sizes
++ *
++ * The stack sizes are set up in start.S using the settings below
++ */
++#define CONFIG_STACKSIZE         (128*1024) /* regular stack */
++
++#endif /* __CONFIG_H */
++
+diff -uNr x-load-f243938.orig/lib/board.c x-load-f243938/lib/board.c
+--- x-load-f243938.orig/lib/board.c	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/lib/board.c	2012-06-07 14:45:39.457648667 -0300
+@@ -49,8 +49,10 @@
+ static int init_func_i2c (void)
+ {
+ #ifdef CONFIG_MMC
++#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ 	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+ #endif
++#endif
+ 	return 0;
+ }
+ 
+@@ -65,8 +67,10 @@
+ 	print_info,
+   	nand_init,		/* board specific nand init */
+ #ifdef CONFIG_MMC
++#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+ 	init_func_i2c,
+ #endif
++#endif
+   	NULL,
+ };
+ 
+@@ -87,6 +91,7 @@
+ 	misc_init_r();
+ 
+ 	buf =  (uchar*) CFG_LOADADDR;
++	*(int *)buf = 0xffffffff;
+ 
+ #ifdef CONFIG_MMC
+ 	/* first try mmc */
+@@ -104,6 +109,7 @@
+ 	if (buf == (uchar *)CFG_LOADADDR) {
+ 		/* if no u-boot on mmc, try onenand or nand, depending upon sysboot */
+ 		if (get_mem_type() == GPMC_ONENAND){
++#ifdef CFG_ONENAND
+ #ifdef CFG_PRINTF
+        			printf("Loading u-boot.bin from onenand\n");
+ #endif
+@@ -111,7 +117,9 @@
+         			if (!onenand_read_block(buf, i))
+         				buf += ONENAND_BLOCK_SIZE;
+         		}
++#endif
+ 		} else if (get_mem_type() == GPMC_NAND){
++#ifdef CFG_NAND_K9F1G08R0A
+ #ifdef CFG_PRINTF
+        			printf("Loading u-boot.bin from nand\n");
+ #endif
+@@ -119,6 +127,7 @@
+         			if (!nand_read_block(buf, i))
+         				buf += NAND_BLOCK_SIZE; /* advance buf ptr */
+         		}
++#endif
+ 		}
+ 	}
+ 
+diff -uNr x-load-f243938.orig/Makefile x-load-f243938/Makefile
+--- x-load-f243938.orig/Makefile	2010-08-03 18:08:38.000000000 -0300
++++ x-load-f243938/Makefile	2012-06-07 14:45:39.437648667 -0300
+@@ -84,6 +84,12 @@
+ 
+ all:		$(ALL)
+ 
++ift:	$(ALL) x-load.bin.ift
++
++x-load.bin.ift: signGP System.map x-load.bin
++	TEXT_BASE=`grep -w _start System.map|cut -d ' ' -f1`
++	./signGP x-load.bin $(TEXT_BASE)
++	cp x-load.bin.ift MLO
+  
+ x-load.bin:	x-load
+ 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+@@ -106,6 +112,9 @@
+ oneboot:	x-load.bin
+ 		scripts/mkoneboot.sh
+ 
++signGP:		scripts/signGP.c
++		gcc -O3 -o signGP  $<
++
+ #########################################################################
+ else
+ all install x-load x-load.srec oneboot depend dep:
+@@ -157,6 +166,12 @@
+ 	@./mkconfig $(@:_config=) arm omap3 omap3530beagle
+ 
+ #########################################################################
++## OMAP4 (ARM-CortexA9) Systems
++#########################################################################
++omap4430panda_config :    unconfig
++	@./mkconfig $(@:_config=) arm omap4 omap4430panda
++
++#########################################################################
+ 
+ clean:
+ 	find . -type f \
+@@ -171,7 +186,7 @@
+ 		| xargs rm -f
+ 	rm -f $(OBJS) *.bak tags TAGS
+ 	rm -fr *.*~
+-	rm -f x-load x-load.map $(ALL) 
++	rm -f x-load x-load.map $(ALL) x-load.bin.ift signGP MLO
+ 	rm -f include/asm/proc include/asm/arch
+ 
+ mrproper \
+diff -uNr x-load-f243938.orig/scripts/signGP.c x-load-f243938/scripts/signGP.c
+--- x-load-f243938.orig/scripts/signGP.c	1969-12-31 21:00:00.000000000 -0300
++++ x-load-f243938/scripts/signGP.c	2012-06-07 14:45:39.461648667 -0300
+@@ -0,0 +1,280 @@
++//
++// signGP.c
++// Read the x-load.bin file and write out the x-load.bin.ift file.
++// The signed image is the original pre-pended with the size of the image
++// and the load address.  If not entered on command line, file name is
++// assumed to be x-load.bin in current directory and load address is
++// 0x40200800.
++
++#include <stdio.h>
++#include <stdlib.h>
++#include <fcntl.h>
++#include <sys/stat.h>
++#include <string.h>
++#include <malloc.h>
++#include <linux/types.h>
++
++#undef CH_WITH_CHRAM
++struct chsettings {
++	__u32 section_key;
++	__u8 valid;
++	__u8 version;
++	__u16 reserved;
++	__u32 flags;
++} __attribute__ ((__packed__));
++
++/*    __u32  cm_clksel_core;
++    __u32  reserved1;
++    __u32  cm_autoidle_dpll_mpu;
++    __u32  cm_clksel_dpll_mpu;
++    __u32  cm_div_m2_dpll_mpu;
++    __u32  cm_autoidle_dpll_core;
++    __u32  cm_clksel_dpll_core;
++    __u32  cm_div_m2_dpll_core;
++    __u32  cm_div_m3_dpll_core;
++    __u32  cm_div_m4_dpll_core;
++    __u32  cm_div_m5_dpll_core;
++    __u32  cm_div_m6_dpll_core;
++    __u32  cm_div_m7_dpll_core;
++    __u32  cm_autoidle_dpll_per;
++    __u32  cm_clksel_dpll_per;
++    __u32  cm_div_m2_dpll_per;
++    __u32  cm_div_m3_dpll_per;
++    __u32  cm_div_m4_dpll_per;
++    __u32  cm_div_m5_dpll_per;
++    __u32  cm_div_m6_dpll_per;
++    __u32  cm_div_m7_dpll_per;
++    __u32  cm_autoidle_dpll_usb;
++    __u32  cm_clksel_dpll_usb;
++    __u32  cm_div_m2_dpll_usb;
++}*/
++
++struct gp_header {
++	__u32 size;
++	__u32 load_addr;
++} __attribute__ ((__packed__));
++
++struct ch_toc {
++	__u32 section_offset;
++	__u32 section_size;
++	__u8 unused[12];
++	__u8 section_name[12];
++} __attribute__ ((__packed__));
++
++struct chram {
++	/*CHRAM */
++	__u32 section_key_chr;
++	__u8 section_disable_chr;
++	__u8 pad_chr[3];
++	/*EMIF1 */
++	__u32 config_emif1;
++	__u32 refresh_emif1;
++	__u32 tim1_emif1;
++	__u32 tim2_emif1;
++	__u32 tim3_emif1;
++	__u32 pwrControl_emif1;
++	__u32 phy_cntr1_emif1;
++	__u32 phy_cntr2_emif1;
++	__u8 modereg1_emif1;
++	__u8 modereg2_emif1;
++	__u8 modereg3_emif1;
++	__u8 pad_emif1;
++	/*EMIF2 */
++	__u32 config_emif2;
++	__u32 refresh_emif2;
++	__u32 tim1_emif2;
++	__u32 tim2_emif2;
++	__u32 tim3_emif2;
++	__u32 pwrControl_emif2;
++	__u32 phy_cntr1_emif2;
++	__u32 phy_cntr2_emif2;
++	__u8 modereg1_emif2;
++	__u8 modereg2_emif2;
++	__u8 modereg3_emif2;
++	__u8 pad_emif2;
++
++	__u32 dmm_lisa_map;
++	__u8 flags;
++	__u8 pad[3];
++} __attribute__ ((__packed__));
++
++
++struct ch_chsettings_chram {
++	struct ch_toc toc_chsettings;
++	struct ch_toc toc_chram;
++	struct ch_toc toc_terminator;
++	struct chsettings section_chsettings;
++	struct chram section_chram;
++	__u8 padding1[512 -
++		    (sizeof(struct ch_toc) * 3 +
++		     sizeof(struct chsettings) + sizeof(struct chram))];
++	//struct gp_header gpheader;
++} __attribute__ ((__packed__));
++
++struct ch_chsettings_nochram {
++	struct ch_toc toc_chsettings;
++	struct ch_toc toc_terminator;
++	struct chsettings section_chsettings;
++	__u8 padding1[512 -
++		    (sizeof(struct ch_toc) * 2 +
++		     sizeof(struct chsettings))];
++	//struct gp_header gpheader;
++} __attribute__ ((__packed__));
++
++
++#ifdef CH_WITH_CHRAM
++const struct ch_chsettings_chram config_header = {
++	//CHSETTINGS TOC
++	{sizeof(struct ch_toc) * 4,
++	 sizeof(struct chsettings),
++	 "",
++	 {"CHSETTINGS"}
++	 },
++	//CHRAM TOC
++	{sizeof(struct ch_toc) * 4 + sizeof(struct chsettings),
++	 sizeof(struct chram),
++	 "",
++	 {"CHRAM"}
++	 },
++	// toc terminator
++	{0xFFFFFFFF,
++	 0xFFFFFFFF,
++	 {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++	  0xFF},
++	 {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++	  0xFF}
++	 },
++	//CHSETTINGS section
++	{
++	 0xC0C0C0C1,
++	 0,
++	 1,
++	 0,
++	 0},
++	//CHRAM section
++	{
++	 0xc0c0c0c2,
++	 0x01,
++	 {0x00, 0x00, 0x00},
++
++	 /*EMIF1 */
++	 0x80800eb2,
++	 0x00000010,
++	 0x110d1624,
++	 0x3058161b,
++	 0x030060b2,
++	 0x00000200,
++	 0x901ff416,
++	 0x00000000,
++	 0x23,
++	 0x01,
++	 0x02,
++	 0x00,
++
++	 /*EMIF2 */
++	 0x80800eb2,
++	 0x000002ba,
++	 0x110d1624,
++	 0x3058161b,
++	 0x03006542,
++	 0x00000200,
++	 0x901ff416,
++	 0x00000000,
++	 0x23,
++	 0x01,
++	 0x02,
++	 0x00,
++
++	 /* LISA map */
++	 0x80700100,
++	 0x05,
++	 {0x00, 0x00, 0x00},
++	 },
++	""
++};
++#else
++struct ch_chsettings_nochram config_header  __attribute__((section(".config_header"))) = {
++	//CHSETTINGS TOC
++	{(sizeof(struct ch_toc)) * 2,
++	 sizeof(struct chsettings),
++	 "",
++	 {"CHSETTINGS"}
++	 },
++	// toc terminator
++	{0xFFFFFFFF,
++	 0xFFFFFFFF,
++	 {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++	  0xFF},
++	 {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
++	  0xFF}
++	 },
++	//CHSETTINGS section
++	{
++	 0xC0C0C0C1,
++	 0,
++	 1,
++	 0,
++	 0},
++	""
++};
++#endif
++
++
++main(int argc, char *argv[])
++{
++	int	i;
++	char	ifname[FILENAME_MAX], ofname[FILENAME_MAX], ch;
++	FILE	*ifile, *ofile;
++	unsigned long	loadaddr, len;
++	struct stat	sinfo;
++
++
++	// Default to x-load.bin and 0x40200800.
++	strcpy(ifname, "x-load.bin");
++	loadaddr = 0x40200800;
++
++	if ((argc == 2) || (argc == 3))
++		strcpy(ifname, argv[1]);
++
++	if (argc == 3)
++		loadaddr = strtoul(argv[2], NULL, 16);
++
++	// Form the output file name.
++	strcpy(ofname, ifname);
++	strcat(ofname, ".ift");
++
++	// Open the input file.
++	ifile = fopen(ifname, "rb");
++	if (ifile == NULL) {
++		printf("Cannot open %s\n", ifname);
++		exit(0);
++	}
++
++	// Get file length.
++	stat(ifname, &sinfo);
++	len = sinfo.st_size;
++
++	// Open the output file and write it.
++	ofile = fopen(ofname, "wb");
++	if (ofile == NULL) {
++		printf("Cannot open %s\n", ofname);
++		fclose(ifile);
++		exit(0);
++	}
++
++	// Pad 1 sector of zeroes.
++	//ch = 0x00;
++	//for (i=0; i<0x200; i++)
++	//	fwrite(&ch, 1, 1, ofile);
++
++	fwrite(&config_header, 1, 512, ofile);
++	fwrite(&len, 1, 4, ofile);
++	fwrite(&loadaddr, 1, 4, ofile);
++	for (i=0; i<len; i++) {
++		fread(&ch, 1, 1, ifile);
++		fwrite(&ch, 1, 1, ofile);
++	}
++
++	fclose(ifile);
++	fclose(ofile);
++}
-- 
1.7.9.5

