From: Rouven Czerwinski <r.czerwinski@pengutronix.de>
To: ptxdist@pengutronix.de
Cc: Rouven Czerwinski <r.czerwinski@pengutronix.de>
Subject: [ptxdist] [PATCH v3 1/2] architecture: add riscv support
Date: Mon, 30 Jul 2018 07:45:53 +0200 [thread overview]
Message-ID: <20180730054554.23687-2-r.czerwinski@pengutronix.de> (raw)
In-Reply-To: <20180723083343.8583-1-r.czerwinski@pengutronix.de>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
---
platforms/architecture.in | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/platforms/architecture.in b/platforms/architecture.in
index f91fedb08..8fb870eff 100644
--- a/platforms/architecture.in
+++ b/platforms/architecture.in
@@ -125,6 +125,15 @@ choice
select ARCH_SUPPORTS_ENDIAN_BIG
help
This is support for the SuperH architecture.
+
+ config ARCH_RISCV
+ bool "riscv "
+ select HAS_MMU
+ select ARCH_SUPPORTS_ENDIAN_LITTLE
+ select ARCH_LP64
+ help
+ This is support for the RISC-V architecture.
+
endchoice
#
@@ -264,6 +273,7 @@ config HAS_HARDFLOAT
default y if ARCH_X86
default y if ARCH_SPARC
default y if ARCH_ARM64
+ default y if ARCH_RISCV
default n
#
@@ -304,3 +314,4 @@ config ARCH_STRING
default "cris" if ARCH_CRIS
default "parisc" if ARCH_PARISC
default "sh" if ARCH_SH
+ default "riscv" if ARCH_RISCV
--
2.18.0
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next prev parent reply other threads:[~2018-07-30 5:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-23 8:33 [ptxdist] [PATCH " Rouven Czerwinski
2018-07-23 8:33 ` [ptxdist] [PATCH 2/2] platforms/kernel: add riscv Rouven Czerwinski
2018-07-23 12:13 ` [ptxdist] [PATCH v2 1/2] architecture: add riscv support Rouven Czerwinski
2018-07-23 12:13 ` [ptxdist] [PATCH v2 2/2] platforms/kernel: add riscv Rouven Czerwinski
2018-07-25 12:56 ` [ptxdist] [PATCH v2 1/2] architecture: add riscv support Michael Olbrich
2018-07-30 5:45 ` [ptxdist] [PATCH v3 0/2] Add RISC-V support to PTXDIST Rouven Czerwinski
2018-07-30 5:45 ` Rouven Czerwinski [this message]
2018-07-30 5:45 ` [ptxdist] [PATCH v3 2/2] platforms/kernel: add riscv Rouven Czerwinski
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