[ptxdist] rsync3: trap invalid opcode on x86_64 (ptxdist 2023.02.0)

[ptxdist] rsync3: trap invalid opcode on x86_64 (ptxdist 2023.02.0)

[Artur Wiebe]

Hi,

rsync fails with invalid opcode on my x86_64 target:
traps: rsync[245] trap invalid opcode ip:441a40 sp:7ffef7883068 error:0 in rsync[403000+51000]

It works when roll-simd is disabled:
--disable-roll-simd

Are maybe some host CPU flags used in the build which are not present on the target?
Maybe it is better not to enable this by default?

Host-CPU:
model name      : Intel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm cpuid_fault epb invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid xsaveopt dtherm ida arat pln pts md_clear flush_l1d

Target-CPU:
model name      : Intel(R) Atom(TM) CPU N2800   @ 1.86GHz
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl nonstop_tsc cpuid aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm movbe lahf_lm dtherm arat

BR, Artur

Re: [ptxdist] rsync3: trap invalid opcode on x86_64 (ptxdist 2023.02.0)

[Christian Melki]

Hi Artur.

On 2/15/23 21:11, Artur Wiebe wrote:
> Hi,
> 
> rsync fails with invalid opcode on my x86_64 target:
> traps: rsync[245] trap invalid opcode ip:441a40 sp:7ffef7883068 error:0 in rsync[403000+51000]
> 
> It works when roll-simd is disabled:
> --disable-roll-simd
> 

iiuc it looks like rsync tests things locally?
https://github.com/WayneD/rsync/blob/master/configure.ac#L244
Likely to crash and burn on a lot of cross x86_64 builds.

> Are maybe some host CPU flags used in the build which are not present on the target?
> Maybe it is better not to enable this by default?
> 

So yes to both, but one would have to look a little bit deeper than
this. There are a few knobs in configure.

But in general, x86_64 is rather unspecific if that's what you're using
as a target. If you're not limiting the compiler I think it happily
emits whatever looks somewhat sane.

I solve these by doing specified emission of insn towards an arch that
matches the target for x86_64, much like any other arch.

I do that by using a more target specific toolchain. Yes, this yields a
lot of toolchains and tuning in the toolchains rather than options in
ptxdist. End result should be pretty much the same regardless.

But that usually emits sane things unless specified otherwise.
I'd hope that if the compiler sees handwritten intrinsics that don't fly
under what can be emitted for the target, it would puke in those cases. :)

> Host-CPU:
> model name      : Intel(R) Core(TM) i7-4810MQ CPU @ 2.80GHz
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm cpuid_fault epb invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid xsaveopt dtherm ida arat pln pts md_clear flush_l1d
> 
> Target-CPU:
> model name      : Intel(R) Atom(TM) CPU N2800   @ 1.86GHz
> flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl nonstop_tsc cpuid aperfmperf pni dtes64 monitor ds_cpl est tm2 ssse3 cx16 xtpr pdcm movbe lahf_lm dtherm arat
> 

Without using more specific implementation target monikers then the host
looks like a v3 baseline and target is a v1 (or just x86_64). afaict
that is.

> BR, Artur
> 
> 

Regards
Christian