From: Lucas Stach <l.stach@pengutronix.de>
To: ptxdist@pengutronix.de
Subject: Re: [ptxdist] Pin ctrl in devices tree files
Date: Tue, 20 May 2014 10:50:58 +0200 [thread overview]
Message-ID: <1400575858.4853.2.camel@weser.hi.pengutronix.de> (raw)
In-Reply-To: <loom.20140520T094401-697@post.gmane.org>
Am Dienstag, den 20.05.2014, 07:59 +0000 schrieb Sophie:
> Hello,
>
> This question concerns the imx6qdl-tqma6x.dtsi file written by Sascha Hauer,
> Pengutronix, but I don't know if he can answer.
>
> Nevertheless, it could be a more general question : I want to know if the
> 32-bit words programmed in the following lines concern the
> IOMUXC_SW_PAD_CTL_PAD registers that is to say IOMUXC_SW_PAD_CTL_PAD_GPIO5
> and IOMUXC_SW_PAD_CTL_PAD_GPIO6 registers (Cf. theIMX6SDL Reference Manuel).
>
> Because in the Reference Manuel bits 31-17 are reserved and always 0. Why is
> there a '4' in these bits ? Or is it another register ?
>
> -----------------------------------------------------------------------
>
> i2c3 {
> pinctrl_i2c3_2: i2c3grp-2 {
> fsl,pins = <
> MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
> MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> >;
> };
> };
>
Please look at
Documentation/devicetree/bindings/pinctrl/fsl,imx6q-pinctrl.txt to see
what those values are supposed to mean.
Regards,
Lucas
--
Pengutronix e.K. | Lucas Stach |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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prev parent reply other threads:[~2014-05-20 8:52 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-20 7:59 Sophie
2014-05-20 8:50 ` Lucas Stach [this message]
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